Introduction to Processing

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless breakthroughs and developments in wafer fab processing. Today’s wafer fab contains some of the most complex and intricate procedures ever developed by mankind. Introduction to Processing is a 2-day course that offers an overview look into the semiconductor manufacturing process, and the individual processing technologies required to make them. We place special emphasis on the basics surrounding each technique, and we summarize the current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.

By focusing on the basics of each processing step and the issues surrounding them, participants will learn why certain techniques are preferred over others. Our instructors work hard to explain how semiconductor processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

Register for this Course

Course Dates | Location

June 3-4, 2019 | San Jose, CA, USA
(Price available until Mon. May 13)

1-Year Online Training Subscription
(Includes this and other materials.)

Cost

$1,295
$1,195

$500

Pay Via Purchase Order/Check

Please fax the printable registration form for public courses to us at 1-866-205-0713 to complete your order.

Additional Information

For dates and locations in South East Asia, please contact us at se-asia.courses@semitracks.com.

Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

Can't attend this course due to work schedule or lack of travel budget? An Online version of this course is available in our Online Training System!

What Will I Learn By Taking This Class?

Participants learn basic but powerful aspects about the semiconductor industry. This skill-building series is divided into four segments:

  1. Basic Processing Steps. Each processing step addresses a specific need in IC creation. Participants learn the fundamentals of each processing step and why they are used in the industry today.
  2. The Evolution of Each Processing Step. It is important to understand how wafer fab processing came to the point where it is today. Participants learn how each technique has evolved for use in previous and current generation ICs.
  3. Current Issues in Wafer Fab Processing. Participants learn how many processing steps are increasingly constrained by physics and materials science. They also learn about the impact of using new materials in the fabrication process and how those materials may create problems for the manufacturers in the future.
  4. Current Issues in Assembly and Packaging. Participants learn how packaging is a key enabler for semiconductor components. They also learn why we are seeing an explosion of different packaging types.

Course Objectives

  1. The seminar will provide participants with an overview of the semiconductor industry and its technical issues.
  2. Participants will understand the basic concepts behind the fundamental wafer fab processing steps.
  3. The seminar will identify the key issues related to each of the processing techniques and their impact on the continued scaling of the semiconductor industry.
  4. Participants will be able to identify the basic features and principles associated with each major processing step. These include processes like chemical vapor deposition, ion implantation, lithography, and etching.
  5. Participants will understand how processing, reliability, power consumption and device performance are interrelated.
  6. Participants will be able to make decisions about how to construct and evaluate processing steps for CMOS, BiCMOS, and bipolar technologies.
  7. The seminar will provide an introduction to the packaging process and discuss the fundamental drivers behind the current developments in packaging.

Course Outline

Day 1

  1. Raw Silicon Wafers
  2. Ion Implantation
  3. Thermal Processing
  4. Contamination Monitoring and Control
  5. Wafer Cleaning and Surface Preparation
  6. Chemical Vapor Deposition
  7. Physical Vapor Deposition
  8. Lithography
  9. Etch
  10. Chemical Mechanical Polishing
  11. Cu Interconnect and low-k Dielectrics

Day 2

  1. Leading Edge Technologies and Techniques
    1. ALD
    2. High-k gate and capacitor dielectrics
    3. Metal gates
    4. SOI
    5. Strained silicon
    6. Plasma doping
  2. Overview of Semiconductor Packaging
    1. Purpose of the package
    2. Drivers
    3. Types of Packages
    4. Packaging Processes

Instructional Strategy

By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor processing and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field. The accompanying textbook offers hundreds of pages of additional reference material participants can use back at their daily activities.

Instructor Profile

Dr. Jeffrey Gambino

Jeffrey Gambino

Dr. Gambino received his B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and his Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM's Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM's manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology. He has published over 90 technical papers and holds over 100 patents.