Test

This workspace covers semiconductor and integrated circuit test. Test is a critical aspect of the design and manufacturing process. Test allows one to determine if the device is working correctly, and it can also give insight into potential failure mechanisms and manufacturing issues. In this section we cover: defect modeling, design for test, digital testing, analog testing, parametric testing, and test hardware.

Register for an Account

Item

1-Year Online Training Subscription
(Includes this and other materials.)

Cost

$500

Pay Via Credit Card

Add To Shopping Cart

Pay Via Purchase Order/Check

Please fax the printable registration form for online training to us at 1-866-205-0713 to complete your order.

Additional Information

Refund Policy

Defect Based Testing

Defect-based testing is the practice of testing with the idea of detecting defective conditions on complex ICs. Defect-based testing moves beyond functional and structural testing by introducing test concepts to catch actual defects. Many defects are not easily caught with standard test techniques, and require additional test approaches. Defect-based testing incorporates knowledge of defects like opens, shorts, resistive connections, parametric anomalies, and process variation-induced problems. It requires an understanding of the electrical behavior of these defects. The electrical behavior can be turned into a defect model, which in turn leads to effective test approaches like at-speed testing, delay testing, IDDQ testing and low voltage testing. These are test strategies that are used in conjunction with standard functional and structural test. These test approaches also require an understanding of automatic test pattern generation (ATPG), since one must generate vector sets to catch these problems. Defect-based testing also is critical for failure analysis troubleshooting activities. Defect diagnosis uses these concepts and test techniques to help automatically detect defects.

Presentations

Introduction to Defect-Oriented Testing

ATPG Basics

ATPG Algorithms

Basic ATPG Diagnosis

CMOS Defect Mechanisms and Detection Overview

CMOS Opens and Detection Techniques

CMOS Shorts and Detection Techniques

Defect Classes

Detection Techniques for CMOS Defects

Failure Mechanisms in CMOS IC Materials

Parametric Defects and Detection Techniques

Documents

Introduction to Defect-Oriented Testing

ATPG Basics

Basic ATPG Diagnosis

CMOS Defect Mechanisms and Detection Overview

CMOS Opens and Detection Techniques

Detection Techniques for CMOS Defects

Failure Mechanisms in CMOS IC Materials

Videos

NONE

Test Basics

This material covers basic issues in test. Currently, this course contains an introduction to automatic test and an overview of boundary scan test techniques.

Presentations

Automatic Testing Overview

Boundary Scan Overview

Test Engineering Overview

Test Engineering Equipment

Analog Design for Test - Overview

Continuity Testing

Current Testing

Leakage Testing

Digital Design for Test

Loadboard Hardware Components

Loadboard Hardware Design Flow

Test Economics

Documents

Automatic Testing Overview

Boundary Scan Overview

Videos

NONE

Test Methodologies

This course material covers test methodologies for ICs. It includes information on digital testing, current testing, and timing tests. All three are useful to help localize defects and other problems on circuits prior to shipping them to the customer.

Presentations

Test Process Basics

IDDx Testing

Low Voltage Test

Timing Tests in Production

Documents

Low Voltage Test

Videos

NONE

Design for Test

Design For Test, also known as DFT, encompasses a set of activities that designers normally do to help aid in the testing of ICs. Complex circuits can be quite difficult to test in a thorough manner, so engineers plan for the testing by designing the circuit in such a way so that the test engineers can achieve high test coverage with minimal test costs. DFT encompasses activities like design partitioning, the use of testable technologies, like low power static CMOS, the inclusion of scan circuits, the use of built-in self test or BIST, and other aids.

Presentations

Analog Design for Test - Overview

Analog DFT - Test Modes

Analog DFT - Other Methods

Documents

NONE

Videos

NONE

Fault Models

This course material covers fault models that are used by engineers to develop test routines for complex chips. A fault model is an abstract concept designed to translate the behavior of a defect into a condition that can be tested, preferably on a digital test system.

Presentations

Fault Models for Defect-Based Test

Bridging Fault Models

Delay Fault Models

Fault Diagnosis Algorithms

Fault Dictionaries

Stuck-At-Fault Testing

Documents

Fault Models for Defect-Based Test

Delay Fault Models

Stuck-At-Fault Testing

Videos

NONE