Packaging Design

This material covers the electrical behavior, thermal properties, and the structural and mechanical aspects of electronic packaging. As packaging technology increases in complexity, a whole host of electrical, thermal, and mechanical issues must be accounted for and modeled. The electrical issues include resistance, capacitance, cross talk issues, power and ground bus disturbances, and high frequency packaging. Thermal issues include heat dissipation, the uses of ceramic and plastic, actively cooled packages, heat sinks and planes, and materials issues. Mechanical include thermal coefficient of expansion issues, plastic vs. ceramic packaging, as well as soldering issues. This material also covers the modeling techniques used to characterize these issues.

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Packaging Design

Introduction

Presentations

Introduction to Packaging Modeling and Simulation

Course and Instructor Overview

Documents

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Videos

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Assembly Process

Introduction

This section contains an overview of the assembly process as well as some more detailed presentations on the assembly process. The assembly process normally includes such steps as Wafer Dicing, Die Attach to the Leadframe, the Wirebonding Process, the Mold Injection Process, Singulation, Trim and Form, and for Ball Grid Array (BGA) devices, the Redistribution Layer and Bump (sometimes just simplified as "Bump") Process.

Presentations

Assembly and Packaging Processes Introduction

Documents

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Videos

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Packaging Elements

Introduction

Packaging elements includes information on the individual materials and structures used in semiconductor packages. This includes packaging elements like the leadframes, mold compounds, substrates, interposers, solder balls, copper pillars, and redistribution layers. We discuss each of these topics in more detail.

Presentations

Transfer Molding

Through Silicon Vias

Documents

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Videos

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Package Types

Introduction

Packaging is one of the most active areas for development in the semiconductor industry right now. Someone recently estimated that there are more than 40,000 different package types currently on the market. In this course we will cover the more common package type families. These include: Standard Leaded Packages, Flip Chip Packages, Chip Scale Packages, Wafer Level Packages, Stacked Die Packages and Stacked Packages.

Presentations

Package Types

Flip Chip Packages

Chip Scale Packages

Wafer Level Packages

Stacked Die Packages

Stacked Packages

Documents

Chip Scale Packages

Videos

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Packaging Design Concepts

Introduction

Today's packages can have significant interactions with the die, so some thought is required when designing a new package. This course covers some of those topics. We begin with some high-level package design principles. Basically, the package is used for electrical connections between the die and the system, removing heat, mechanical integrity, to protect the die from damage, to create a format that can be used by the electronics manufacturer. In advanced ICs, engineers actually design the package at the same time as the die, an activity known as chip-package co-design, and this topic is discussed here as well.

Presentations

Package Design Principles

Solid Mechanics Concepts

Documents

Chip and Package Co-Design

Videos

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Packaging Drivers

Introduction

Like much of the semiconductor industry, the semiconductor package developments come out of a number of drivers. The biggest drivers include cost, weight and size. Many of these drivers are captured by the International Technology Roadmap for Semiconductors (ITRS). Other drivers include manufacturability and reliability. These drivers are captured in part by the Joint Electron Device Engineering Council (JEDEC). JEDEC creates standards around package manufacturability and reliability, and we discuss that in this course.

Presentations

Packaging Business Issues

Packaging Engineering and the Electronics Ecosystem

The ITRS and Its Impact on Packaging Design and Modeling

JEDEC Packaging Standards

Documents

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Videos

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