Advanced CMOS/FinFET Fabrication

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The question looming in everyone’s mind is “How far into the future can this continue?” Advanced CMOS/FinFET Fabrication is a 1-day course that offers detailed instruction on the processing used in a modern integrated circuit, and the processing technologies required to make them. We place special emphasis on current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.

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Course Dates | Location

February 6, 2017 | Portland, OR, USA

Cost

$695

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Please fax the printable registration form for public courses to us at 1-866-205-0713 to complete your order.

Additional Information

For dates and locations in South East Asia, please contact us at se-asia.courses@semitracks.com.

Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

By concentrating on the latest developments in CMOS and FinFET technology, participants will learn why FinFETs and FD-SOI are fast becoming the technologies of choice at feature sizes below 20nm. Our instructors work hard to explain semiconductor processing without delving heavily into the complex physics and materials science that normally accompany this discipline.

Participants learn basic but powerful aspects about FinFET technology. This skill-building series is divided into four segments:

  1. Front End Of Line (FEOL) Overview. Participants study the major developments associated with FEOL processing, including ion implantation, Rapid Thermal Annealing (RTA) for implants and silicides, and Pulsed Plasma Doping. They also study alternate substrate technologies like SOI as well as High-k/Metal Gates for improved leakage control.
  2. Back End Of Line (BEOL) Overview. Participants study the major developments associated with BEOL processing, including copper metallization and Low-k Dielectrics. They learn about why they’re necessary for improved performance.
  3. FinFET Manufacturing Overview. Participants learn how semiconductor manufacturers are currently processing FinFET devices and the difficulties associated with three-dimensional structures from a processing and metrology standpoint.
  4. FinFET Reliability. They also study the failure mechanisms and techniques used for studying the reliability of these devices.

Course Objectives

  1. The seminar will provide participants with an in-depth understanding of SOI technology and the technical issues.
  2. Participants will understand how Hi-K/Metal Gate devices are manufactured.
  3. Participants will also understand how FinFET devices are manufactured.
  4. The seminar provides a look into the lastest challenges with copper metallization and Low-k dielectrics.
  5. Participants will understand the difficulties associated with non-planar structures and methods to alleviate the problems.
  6. Participants will be able to make decisions about how to evaluate FinFET devices and what changes are likely to emerge in the coming years.
  7. Participants will briefly learn about IC reliability and the failure modes associated with these devices.
  8. Finally, the participants see a comparison between FD-SOI (the leading alternative) and FinFETs.

Course Outline

Day 1

  1. Advanced CMOS Fabrication – Introduction
  2. Front End Of Line (FEOL) Processing
    1. SOI and FD-SOI
    2. Ion Implantation and Rapid Thermal Annealing
    3. Pulsed Plasma Doping
    4. Hi-K/Metal Gates
    5. Processing Issues
      1. Lithography
      2. Etch
      3. Metrology
  3. Back End Of Line (BEOL) Processing
    1. Introduction and Performance Issues
    2. Copper
      1. Deposition Methods
      2. Liners
      3. Capping Materials
      4. Damascene Processing Steps
    3. Lo-k Dielectrics
      1. Materials
      2. Processing Methods
    4. Reliability Issues
  4. FinFET Manufacturing Overview
    1. Substrates
      1. Bulk
      2. SOI
    2. FinFET Types
    3. Process Sequence
    4. Processing Issues
      1. Lithography
      2. Etch
      3. Metrology
  5. FinFET Reliability
    1. Defect density issues
    2. Gate Stack
    3. Transistor Reliability (BTI and Hot Carriers)
    4. Heat dissipation issues
    5. Failure analysis challenges
  6. Future Directions for FinFETs
    1. Comparison of FD-SOI and FinFETs – Are FinFETs a better choice?
    2. Scaling

Instructional Strategy

By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor processing and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field. The accompanying textbook offers hundreds of pages of additional reference material participants can use back at their daily activities.

Instructor Profile

Dr. Jeffrey Gambino

Jeffrey Gambino

Dr. Gambino received his B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and his Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM's Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM's manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology. He has published over 90 technical papers and holds over 100 patents.