EOS, ESD and How to Differentiate

Electrical Overstress (EOS) and Electrostatic Discharge (ESD) account for most of the field failures observed in the electronics industry. Although EOS and ESD damage can at times look quite similar to each other, the source each and the solution can be quite different. Therefore, it is important to be able to distinguish between the two mechanisms. The semiconductor industry needs knowledgeable engineers and scientists to understand these issues. EOS, ESD, and How to Differentiate is a 2-day course that offers detailed instruction on EOS, ESD and how to distinguish between them. This course is designed for every manager, engineer, and technician concerned with EOS, ESD, analyzing field returns, determining impact, and developing mitigation techniques.

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$1,295

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Please fax the printable registration form for public courses to us at 1-866-205-0713 to complete your order.

Additional Information

For dates and locations in South East Asia, please contact us at se-asia.courses@semitracks.com.

Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

Participants learn to develop the skills to determine what constitutes a good ESD design, how to recognize devices that can reduce ESD susceptibility, and how to design new ESD structures for a variety of technologies.

  1. Overview of the EOS Failure Mechanism. Participants learn the fundamentals of EOS, the physics behind overstress conditions, test equipment, sources of EOS, and the results of failure.
  2. Overview of the ESD Failure Mechanism. Participants learn the fundamentals of ESD, the physics behind overstress conditions, test equipment, test protocols, and the results of failure.
  3. ESD Circuit Design Issues. Participants learn how designers develop circuits to protect against ESD damage. This includes MOSFETs, diodes, off-chip driver circuits, receiver circuits, and power clamps.
  4. How to Differentiate. Participants learn how to tell the difference between EOS and ESD. They learn how to simulate damage and interpret pulse widths, amplitudes and polarity.
  5. Resolving EOS/ESD on the Manufacturing Floor. Participants see a number of common problems and their origins.

Course Objectives

  1. The seminar will provide participants with an in-depth understanding of electrical overstress, the models used for EOS, and the manifestation of the mechanism.
  2. Participants will understand the ESD failure mechanism, test structures, equipment, and testing methods used to achieve robust ESD resistance in today's components.
  3. The seminar will identify the major issues associated with ESD, and explain how they occur, how they are modeled, and how they are mitigated.
  4. Participants will be able to identify basic ESD structures and how they are used to help reduce ESD susceptibility on semiconductor devices.
  5. Participants will be able to distinguish between EOS and ESD when performing a failure analysis.
  6. Participants will be able to estimate a pulse width, pulse amplitude, and determine the polarity of an EOS or ESD event.
  7. Participants will see examples of common problems that result in EOS and ESD in the manufacturing environment.

Course Outline

Day 1

  1. Introduction
    1. Terms and Definitions
    2. ESD Fundamentals
    3. EOS Fundamentals
  2. Electrical Overstress Device Physics
    1. Sources of EOS
    2. EOS Models
    3. Electrothermal Physics
  3. Electrostatic Discharge Device Physics
    1. ESD Models
    2. ESD Testing and Qualification
    3. ESD Failure Criteria
    4. Electrothermal Physics
    5. Electrostatic Discharge Failure Models
    6. Semiconductor Devices and ESD Models
    7. Latchup
  4. EOS Issues in Manufacturing
    1. Charging Associated with Equipment
      1. Testers
      2. Automated Handling Equipment
      3. Soldering Irons
    2. Charge Board Events
    3. Cable Discharge Events
    4. Ground Loops/Faulty Wiring
    5. Voltage Differentials due to High Current
    6. Event Detection

Day 2

  1. ESD Protection Methods
    1. Semiconductor Process Methods
    2. MOSFET Design
    3. Diode Design
    4. Off-Chip Drivers
    5. Receiver Networks
    6. Power Clamps
  2. Differentiating Between EOS and ESD
    1. EOS Manifestation
    2. ESD Manifestation
    3. Circuit considerations
      1. Chip level
      2. System level
    4. Simulating ESD
    5. Simulating EOS
  3. EOS/ESD Design and Modeling Tools
    1. Electrothermal Circuit Design
    2. Electrothermal Device Design
    3. ESD CAD Design

Instructional Strategy

By using a combination of instruction by lecture, written text material, problem solving and question/answer sessions, participants will learn practical approaches to the failure analysis process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field. The course notes offer dozens of pages of additional reference material the participants can use back at their daily activities.

Instructor Profile

Christopher Henderson, President of Semitracks

Christopher Henderson

Christopher Henderson received his B.S. in Physics from the New Mexico Institute of Mining and Technology and his M.S.E.E. from the University of New Mexico. Chris is the President and one of the founders of Semitracks Inc., a United States-based company that provides education and semiconductor training to the electronics industry.

From 1988 to 2004, Chris worked at Sandia National Laboratories, where he was a Principal Member of Technical Staff in the Failure Analysis Department and Microsystems Partnerships Department. His job responsibilities have included failure and yield analysis of components fabricated at Sandia's Microelectronics Development Laboratory, research into the electrical behavior of defects, and consulting on microelectronics issues for the DoD. He has published over 20 papers at various conferences in semiconductor processing, reliability, failure analysis, and test. He has received two R&D 100 awards and two best paper awards. Prior to working at Sandia, Chris worked for Honeywell, BF Goodrich Aerospace, and Intel. Chris is a member of IEEE and EDFAS (the Electron Device Failure Analysis Society).

At Semitracks, Chris teaches courses on failure and yield analysis, semiconductor reliability, and other aspects of semiconductor technology.