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What is Mechanical Probe Isolation?

Mechanical probe isolation is the process of selectively removing circuitry away from an I/O port to determine the cause of excess leakage on the structure. The idea is that if structures that are connected to the I/O are removed carefully, the leakage will go away when the offending circuitry is removed. Removal can be done in several ways. The best, but also the most costly is to use a focused ion beam system (FIB). This provides probably the best cut, but does not allow for electrical connection to monitor the I/O port before and after the cut is made. This means that the sample will have to be taken in and out of the FIB several times before the process is complete. The other methods, an ultrasonic cutter or a laser, allow monitoring the leakage on the I/O as the cut is made providing instant feedback when the leaky circuit is removed. These methods are also more cost effective than the FIB.

Why Perform Mechanical Probe Isolation?

Mechanical probe isolation is an easy to do, inexpensive method to analyze leakages on I/O structures. Since damage to I/O ports is fairly common and can be localized to a small area on an IC, this method has a very high probability of success. There are many types of failures especially on ASIC devices that are very difficult to localize, making diagnosis of the failure difficult. In general, the localizability, diagnoseability, and high probability of success makes this type of analysis worthwhile.

How is Mechanical Probe Isolation Performed?

The best place to start this analysis is with a thorough analysis of the I-V characteristics of the leaky structure. This should be done before the package is altered in any way. Measurement before and after package removal will remove any doubts as to the cause of the failure. The I-V characteristic should be measured with respect to VSS, VDD, and every other pin on the device to check for pin to pin shorts. After the package is removed, the same measurements should be made and compared. Any differences between the before and after curves should be noted.

The second step is to understand the structure of the I/O port. Basically, the same circuit elements are present on most types of ports. Identification of input protection structures, buffers and input gates should be done. A careful analysis of the structure usually will give several possibilities as to the cause of the leakage.

Lastly, start from the most remote or the easiest parts of the I/O port to remove. If possible monitor the I/O characteristic is such a way as to best identify when the leakage has gone away. Carefully remove parts of the port with your chosen method (FIB, ultrasonic cutter, or laser cutter) until either the leakage goes away or there is no other circuitry that can be removed. If possible, use an identical known good IC for comparison or for practice if you need it.

This technique is fairly straightforward and considered a "brute force" type approach, but it can offer an inexpensive, accurate method to positively identify a leaky part of an I/O structure.

Leakage Path in Input Pad with Schmidt Trigger

Perform a series of cuts to isolate the location of the leakage within the I/O cell. Press 'Help' for details on where to make the cuts and in which order to make the cuts. To what feature did you isolate the source of the leakage?

Leakage through input transistors
Leakage through interlevel dielectric
Leakage through inner vdd diode
Leakage through vss diode
Leakage through outer vdd diode
Parasitic transistor leakage

Leakage Path in Input Pad with Driver

Leakage through input transistors
Leakage through interlevel dielectric
Leakage through inner vdd diode
Leakage through vss diode
Leakage through outer vdd diode
Parasitic transistor leakage

Leakage Path in Input Bonding Pad

Leakage through input transistors
Leakage through interlevel dielectric
Leakage through inner vdd diode
Leakage through vss diode
Leakage through outer vdd diode
Parasitic transistor leakage

Leakage Path in Output Bonding Pad

Leakage through output transistors
Leakage through interlevel dielectric

Leakage Path in Buffered Inverted Output Pad

Leakage through output transistors
Leakage through interlevel dielectric

Leakage Path in Tri-State Output Driver

Leakage through input transistors
Leakage through output transistors
Leakage through interlevel dielectric
Leakage through vdd diode
Leakage through vss diode
Parasitic transistor leakage

Isolation of Leakage Path in Buffered Output Pad

Next, perform a series of cuts to isolate the location of the leakage within the I/O cell. Press 'Help' for details on where to make the cuts and in which order to make the cuts. To what feature did you isolate the source of the leakage?

Leakage through output transistors
Leakage through interlevel dielectric

When is Mechanical Probe Isolation Performed?

Since this is a destructive approach, it should only be done after all other non-destructive tests have been completed. A thorough electrical characterization of both the entire IC and the leaky port should be done before doing any destructive analysis. Remember, once the IC has been altered you cannot return it to the way it was (unless you have an FIB and have done something that can be patched). In general, since I/O structures are easily characterized from the external pins on the IC package using simple tests, the decision to proceed will be straightforward.

References on Mechanical Probe Isolation

S. L. Vaughan, "A Failure Analysis Approach to Fault Isolation on Complex Microprocessors and Microcomputers, in Proc of ISTFA, 1991, pp. 145-155.
C. C. Baynes, et al., "Procedures for Probing Underlying Structures in Multi-Layered VLSI Devces While Maintaining Electrical Integrity", in Proc of ISTFA, 1988.
L. C. Patterson, "An Inexpensive Technique to Produce High Quality Probe Tips", in Proc ISTFA, 1987, pp. 149-153.
E. Doyle Jr., B. Moris, Microelectronics Falure Analysis Techniques A Procedural Guide, Ch. III-A, RADC.
J. R. Devaney, G. L. Hill, R. G. Seippel, Failure Analysis Mechanisms, Techniques, and Photo Atlas, Ch. 6, Faliure Recognition and Training Services, Inc., 1986.