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What is Illumination Effects Analysis?

The effects of light on the electrical properties and operation of ICs enable localization and analysis of various types of defects and failure mechanisms. Illumination Effects Analysis techniques can range in complexity from simple methods of scanning the light from a conventional reflected light microscope to more sophisticated methods using a scanning laser microscope. Wavelengths from ultraviolet to infrared can be used, depending upon the type of IC and the defects being analyzed. Electrical effects to be analyzed can range from basic photocurrent I-V measurements to more complex logical behavior changes and logic state control.

Regardless technique sophistication, illumination effects analysis uses photon-generated electron-hole pairs to yield information about IC defects and functionality. When electron-hole pairs are generated near the interface between differently doped regions in an unbiased IC, the charge carriers are separated by the built-in potential between areas with different Fermi levels. Biasing an IC can increase or decrease the Fermi level difference between regions, thereby altering the magnitude of electron-hole pair separation. Illumination effects analysis techniques use the current or voltage changes produced by these separated carriers.

Why Perform Illumination Effects Analysis?

The major advantages of analysis techniques based on illumination effects include the relative ease of electrical connections, no requirement for a vacuum system, and the absence of ionizing radiation effects. Photon probing techniques are normally nondestructive and do not alter the defect or degrade the IC.

How is Illumination Effects Analysis Performed?

Simple illumination effects analysis can be performed by placing the IC on a microscope stage and providing appropriate electrical stimulus, such as the burn-in bias condition. Raster the microscope objective or move the stage so that the light from the objective lens scans across the IC surface. It is usually best to start with the microscope illuminator at a high intensity. Monitor the IC electrical parameter of interest, such as the quiescent power supply current (IDDQ), input leakage current, or logic output. When a change in the parameter is observed, note the physical location of the light beam. If no change is observed, try varying the light beam intensity or device stimulus conditions.

More sophisticated techniques require equipment such as a scanning laser microscope. One such technique is light-induced voltage alteration (LIVA), which can find defects such as interconnection open circuits and pn junction damage. It is also possible to use the beam to image logic and control logic states of sequential circuit elements.

The electrical effects of illumination are easier to use for analysis if the IC has a normal power supply current less that 1 mA. Photon probing techniques may work for ICs with relatively high current, but they have a greater probability of success if the current is below 1 mA. Depending on the design of the IC, some logic states may exhibit significantly higher current that other logic states. Because pullup resistors or depletion load transistors could possibly cause this effect, the anaylst must account for these design features when considering how to electrically stimulate and analyze the IC.

When is Illumination Effects Analysis Performed?

Because it is usually a benign analysis technique, illumination effects analysis can be performed at any point in the analysis process when the IC surface or the back of the IC substrate is exposed (an infrared source must be used for the backside analysis). Due to its benign nature, it should be considered prior to other analysis techniques, such an electron beam probing, that might degrade the IC or alter or destroy the defect or failure mechanism.

References on Illumination Effects Analysis

  1. E.I. Cole Jr, J.M. Soden, J.L. Rife, D.L. Barton, and C.L. Henderson, "Novel Failure Analysis Techniques Using Photon Probing with a Scanning Optical Microscope," Inter. Reliability Physics Symp., pp. 388-398, Apr. 1994.
  2. D.J. Burns and J.M. Kendall, "Imaging latch-up sites in LSI CMOS with a laser photoscanner," in Proc. Int. Reliability Physics Symp., pp. 118-121, 1983.
  3. F.J. Henley, "Logic failure analysis of CMOS VLSI using a laser probe," in Proc. Int. Reliability Physics Symp., pp. 69-75, 1984.
  4. D.E. Sawyer and D.W. Berning, "Laser scanning of MOS IC's reveals internal logic states nondestructively," in Proc. IEEE (Lett.), Vol. 64, pp. 393-394, Nov. 1976.
  5. J.R. Haberer and J.J. Bart, "Charge-induced instability in 709 operational amplifiers," in Proc. Int. Reliability Physics Symp., pp. 106-111, 1972.
  6. K.S. Wills, T. Lewis, G. Billus, and H. Hoang, "Optical beam induced current applications for failure analysis of VLSI devices," in Proc. Int. Symp. Testing and Failure Anal. (ISTFA), pp. 21-26, 1990.
  7. E. Zaroni, G. Spiazzi, G.D. Libera, B. Bonati, M. Muschitello, and C. Canali, "Detection and localization of gate oxide shorts in MOS transistors by optical-beam-induced current," IEEE Trans. Elect. Devices, Vol. 38, No. 2, pp. 417-419, Feb. 1991.
  8. D.J. Burns, M.T. Pronobis, C.A. Eldering, and R.J. Hillman, "Reliability/design assessment by internal node timing margin analysis using laser photocurrent injection," in Proc. Int. Reliability Physics Symp., pp. 76-82, 1984.
  9. T.W. Joseph and B. Bossman, "Infrared laser microscopy of structures on heavily doped silicon," in Proc. Int. Symp. for Testing and Failure Anal. (ISTFA), pp. 1-7, 1992.