ESD Design and Technology (Online Version)

Electrostatic discharge is a 4 Billion (USD) a year problem for the Semiconductor Industry. This problem is likely to grow in the future as smaller devices are susceptible to damage at lower static voltages and latchup under more subtle conditions. Today, circuit designers and process integration engineers require a fundamental knowledge of device physics and electrothermal behavior of I/O structures in order to develop a process that is robust and can withstand the challenges of today’s varied environments in which ICs are fielded. Layout, ESD pulse behavior, semiconductor physics, and device modeling are all required to produce a successful product. Your industry needs competent engineers and scientists to help achieve these goals. ESD Design and Technology is a course that offers detailed instruction on a variety of subjects pertaining to ESD design and technology. This course is designed for every manager, engineer, and technician concerned with ESD at the I/O design level, the chip level, or supplying ESD tools and simulators to the industry.

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1-Year Online Training Subscription

(Includes this and other materials.)

Cost

$700

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Please email the printable registration form for online training to us at the email address on the form to complete your order.

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Interested in a version of this course where you can ask questions in real time? Public and In-House versions of this course are available!

What Will I Learn By Taking This Class?

Participants learn to develop the skills to determine what constitutes a good ESD design, how to recognize devices that can reduce ESD susceptibility, and how to design new ESD structures for a variety of technologies.

Overview of the ESD Failure Mechanism. Participants learn the fundamentals of ESD, the physics behind overstress conditions, test equipment, test protocols, and the results of failure.
ESD Technology Issues. Participants learn the behavior of different IC technologies under various ESD stress conditions. This includes CMOS, bipolar, BiCMOS, SOI GaAs, SiGe, SiGe:C and other strained silicon technologies. Participants also study the response of an IC’s substrates, wells, junctions, dielectric layers, and metallization to ESD.
ESD Circuit Design Issues. Participants learn how designers develop circuits to protect against ESD damage. This includes MOSFETs, diodes, off-chip driver circuits, receiver circuits, and power clamps.
Test Strategies. Participants learn the basics on how to test test structures, design screening tests, and how to perform burn-in testing effectively.

Course Objectives

The seminar will provide participants with an in-depth understanding of the ESD failure mechanism, test structures, equipment, and testing methods used to achieve robust ESD resistance in today’s components.
Participants will be able to gather ESD data, determine how best to plot the data, and make inferences from that data.
The seminar will identify the major issues associated with ESD, explain how they occur, how they are modeled, and how they are mitigated.
The seminar can be offered with several textbooks that cover the topic of ESD in much greater detail. The course author is a recognized expert in the field and has written the definitive textbook series on ESD.
Participants will be able to identify basic ESD structures and how they are used to help reduce ESD susceptibility on semiconductor devices.
Participants will be able to knowledgeably design ESD structures that are appropriate to assure the robustness of a component.
Participants will be able to identify appropriate tools to purchase when starting or expanding ESD test capabilities.

Course Outline

Electrostatic Discharge Device Physics
- ESD Models
- ESD Testing and Qualification
- ESD Failure Criteria
- Electrothermal Physics
- Electrostatic Discharge Failure Models
- Semiconductor Devices and ESD Models
- Latchup
Semiconductor Process and ESD Protection
- Substrates and ESD
- Well Design and ESD
- Junctions, Salicide and ESD
- Dielectrics and ESD
- Aluminum, and Copper Interconnects and ESD
ESD in Advanced Technology
- Silicon on Insulator and ESD
- Silicon Germanium and ESD
- Silicon Germanium Carbon and ESD
- Strained Silicon Devices and ESD
- State-of-the-Art Devices: FinFETS, MuGFETs, Nanotubes and the Future
ESD Fundamentals
- ESD History
- ESD Patents and Publications
- Fundamentals of ESD Design
- What makes ESD Design Unique?
- ESD Design Methods
ESD MOSFET Design
- Single Finger
- Multi-finger
- MOSFET Voltage Distribution Effects
- MOSFET Wiring
- MOSFET Contacts
- MOSFET Ballasting
- MOSFET Segmentation
- MOSFET Ballasting
- MOSFET Gate and Body Coupling
ESD Diode Design
- Diode Anode Design
- Diode Cathode Design
- Diode Wiring Patterns
- Diode Contacts
- Diode String ESD Designs
- Triple Well Diode Design
- BiCMOS Diode Design
- BiCMOS Triple Well Diode Design
ESD Circuits and Design
- Chip Architecture and Synthesis
- Input Node HBM Circuits
- Input Node CDM Circuits
- ESD Power Rail Circuits
- ESD CMOS-Based ESD Networks
- ESD BiCMOS-Based ESD Networks

ESD and Off-Chip Drivers
- TTL, HSTL, GTL and SSTL
- Single FET OCD
- Mixed Voltage Interface OCD
- Floating Well Circuitry
- ESD Protection Tradeoffs
ESD and Receiver Networks
- CMOS Receivers
- CMOS Half Pass Transmission Gates
- CMOS Full Pass Transmission Gates
- CMOS Keeper Network
- CMOS Pseudo-Zero VT Receivers
- CMOS Zero VT Receivers
- BiCMOS Receivers
- BiCMOS Off-Chip Drivers
- BiCMOS Differential Circuits
- RF Circuits
ESD Power Clamps
- Diode ESD Power Clamps
- RC Triggered MOSFET Power Clamps
- Voltage Triggered MOSFET Power Clamps
- Bipolar ESD Power Clamps
- Zener Triggered ESD Power Clamps
- BVCEO Triggered SiGe ESD Power Clamps
- Capacitively-Coupled GaAs Power Clamps
ESD Design Tools
- Electrothermal Circuit Design
- Electrothermal Device Design
- ESD CAD Design