Last month we explored the topic of oxidation and kinetics in thermal processing. We’ll continue our discussion this month. There are three steps in the oxidation model. The first step is the gas transfer of oxygen from the ambient environment to the gas/oxide interface. The second step is the diffusion of oxygen across the oxide layer. The third step is the chemical reaction that occurs at the silicon surface. The equations for each step are shown here.

F1 is the gas transport equation, F2 is the oxide diffusion equation, and F3 is the oxygen/silicon reaction equation. H sub G is the mass transfer coefficient in gas, and H is Henry’s law constant. C star is defined as H times p sub G, where p sub G is the partial pressure of the oxidizing species in the bulk of the gas. D is the diffusivity of the oxidizing species in SiO2 and k sub s is the chemical surface reaction rate constant for oxidation.

In the steady state condition F1 should equal F2 which should also equal F3. When the equations are set equal to one another, one can solve for the concentration at the surface of the oxide and the concentration at the interface between the silicon and the silicon dioxide. When the diffusion constant D is very small, the flux of oxygen through the silicon dioxide is small compared to the reaction rate at the interface. This is known as the diffusion rate controlled case, indicated by the line shown here.

When the diffusion constant D is very large, an ample supply of oxygen can reach the interface. This is a reaction rate controlled case, indicated by the line shown here.

If one solves for equation F3 (the reaction rate at the silicon/silicon dioxide surface) after applying the appropriate boundary conditions, one can obtain a solution for X, or the thickness of the oxide. This is a somewhat complicated differential equation boundary value problem, so we will not work it here. Basically, the thickness can be described under two different conditions: one where the time scale is quite long, and one where the time scale is short. The short time scale describes the initial growth region, or the reaction rate limited case, and the long time scale describes the diffusion limited case. For short times where t plus tau is much less than A squared over 4B, X sub O equals B over A times the quantity t plus tau, where B over A is called the linear rate constant. For very long times where t is much greater than A squared over 4B, X sub O squared equals B times t, where B is called the parabolic rate constant. These are the fundamental pieces of the Deal-Grove oxidation model, which we will cover next. The graph here shows the composite of the two growth regimes, where oxide thickness is plotted against oxidation time.

Scientists have studied thermal oxidation for many years. Bruce Deal and Andrew Grove developed the first model to explain thermal oxidation in the mid-1960s while working at Fairchild Semiconductor. Here we show the basic model, where x is the oxide thickness, B is the parabolic rate constant, B over A is the linear rate constant, and tau is a factor to account for oxide present at the start of the oxidation.

Deal and Grove developed their model to agree with the two regimes, the linear growth regime and the parabolic growth regime. In the linear growth regime, the rate of the oxidation reaction dominates. This regime occurs while the oxide layer is still thin, and diffusion of oxygen to the surface is unimpeded. So if B is much greater than B over A, the Deal-Grove equation reduces to this formula.

In the parabolic growth regime, the diffusion of oxygen to the silicon-silicon dioxide interface is increasingly limited. This regime occurs when the oxide increases beyond 500 angstroms. So in this case, if B over A is much greater than B, the Deal-Grove equation reduces to this formula.

These graphs show the Deal-Grove oxidation model applied to both wet oxidation and dry oxidation examples at various temperatures. We show the experimentally-derived constants in the tables below the graphs. Notice that the Deal-Grove model shows a clear oxidation rate driven regime as well as a diffusion rate limited regime.

This image shows a cross-section of the silicon dioxide growth in a LOCOS (pronounced “low-cos”) technology. In a LOCOS technology, process engineers grow a thermal oxide that serves as the isolation between transistors. A silicon nitride mask prevents the oxidation in the active region areas. Notice that the silicon dioxide has consumed a portion of the silicon, expanding down into the silicon itself. The original silicon surface is shown by the dotted line. There is even some growth of the oxide beneath the edge of the silicon nitride mask.

In conclusion, we discussed thermal oxidation and the kinetics of the reaction. While thermal oxidation is primarily driven by temperature, there are two regimes that also control the growth of the oxide: the oxidation rate-limited, or linear regime, and the diffusion rate-limited, or parabolic regime. Deal and Grove developed a model for thermal oxidation in the mid-1960s, and that model is still the prevailing model to explain and understand the first-order effects associated with oxidation.

Process Capability Index, or Cpk is an important topic for Product and Manufacturing Engineers to know. Cpk is an index in the form of a simple number which measures how close a process in running to its specification limits relatively to the natural variability of the process. The Cpk index is part of a series of indices that measure how much natural variation a process experiences relative to its specification limits and permits the engineer to compare different processes to one another with respect to their overall control. The larger the index number, the less like any particular data point will be outside the specification limits. However, a large index is not necessarily a good thing, so engineers may tighten the limits if there is a large Cpk. If Cpk is too large, one never sees an indication that prompts action to fix or optimize the process.

This table describes the process capability indices and the equations to calculate them. Although there are a number of indices, Cpk is the most popular. Process capability indices assume that one is dealing with normally distributed data, and that may not always be the case. It’s important to remember though that some data might have an upper bound, but no lower bound, or vice-versa. An example of this might be quiescent power supply current (IDDQ), or maximum frequency (Fmax). IDDQ typically has an upper bound, but no lower bound, whereas Fmax typically has a lower bound, but no upper bound.

Let’s use a car and a garage as an analogy. The garage will define the specification limits, and the car will define the output of the process. We show four scenarios with cars and garages. If my car is only a little bit smaller than the garage, then I need to park it right in the middle of the garage (center of the specification) if you want to get all of the car in the garage. This is similar to a Cpk of 1. It is a marginal outcome. If my car is wider than the garage, it does not matter how I try to center it, because it will not fit. This is similar to a Cpk of less than 1. It is an unacceptable outcome. If my car is a lot smaller than the garage, it doesn't matter if I park it exactly in the middle, because it will fit and have plenty of room on either side. This is similar to a Cpk of greater than 1. If I can always park my smaller car in the center and with little variation, then this is equivalent to the highest Cpk value, or a value that is much greater than 1. Cpk describes the relationship between the size of the car, the size of the garage and how far away from the middle of the garage I parked the car.

So what is an acceptable value? Clearly, values that are below 1 will be unacceptable, and a value of 1 will be marginal, but what about larger values?

In general in semiconductor manufacturing, we would like to see values equal to or greater than 2.00. This would constitute excellent process capability. A value of 1.33 would be acceptable, and a value of 1.67 would be good. These numbers will obviously vary depending on the process and the type of testing performed to generate the data. Some procedures like trim tests will have lower Cpks, but that is not necessarily a problem, as the purpose of trimming is to improve Cpk.

**Q: How do you adequately protect high speed signal interfaces like LVDS interfaces from ESD and EOS?**

**A:** This is a difficult task. The problem is that high speed signal interfaces require high performance transistors, which are small and sensitive to overstress. This means that to protect them from overstress events, particularly overstress events like charged device model ESD pulses, one must place resistors on the gates of the input transistors, or in series with the output. Unfortunately, this will slow down the operation of the circuits. This places the designer between a rock and a hard place. If one really needs a combination of high speed with additional protection, then one may need to consider other interface schemes that are not direct electrical connections, like optical connections or RF energy connections.

Please visit http://www.semitracks.com/courses/packaging/ic-packaging-design-and-modeling.php to learn more about this exciting course!

(Click on each item for details).

Product Qualification on January 26-27, 2015 (Mon.-Tues.) in San Jose, CA, USA

Wafer Fab Processing on January 26-29, 2015 (Mon.-Thurs.) in San Jose, CA, USA

EOS, ESD and How to Differentiate on January 28-29, 2015 (Wed.-Thurs.) in San Jose, CA, USA

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