Electron Energy Loss Spectroscopy or EELS is a technique that has been around for some time, but is increasingly used for analysis of fab-related defects. The spatial resolution and sensitivity of the technique allow engineers to examine nanometer-scale defects and anomalies, which is far beyond what one can achieve with Energy Dispersive Spectrometry (EDS). EELS can be performed with the appropriate detector on an electron beam system that can transmit electrons through a sample, such as a scanning transmission electron microscope or a standard transmission electron microscope. EELS operates on the fact that electrons will lose energy as they are transmitted through a sample. The energy loss is specific to different elements, allowing the analyst to obtain information similar to that of energy dispersive x-ray analysis. EELS is more sensitive to light elements than EDS, making it useful for examining oxide and nitride layers, as well as other light elements such as lithium and boron. EELS can generate information in the form of spectra and elemental maps, just like EDS.
The EELS detection system is quite a bit different than the EDS detection system (see Figure 1). The transmitted electrons travel through the sample to the detector, which is mounted beneath the sample. The electrons are focused through an aperture at the entrance to the detector. A magnetic prism bends the electrons toward the energy-selecting slit. The amount of bend is dependent on the energy of the electrons after they exit the sample. The faster they travel, the less they are bent. The electrons are then focused through a quadrupole-sextupole lens arrangement, and then sent to a CCD camera for imaging. This detection system is very sensitive to small changes in electron energy, making it ideal for distinguishing elements. The detection system has the spatial resolution of the TEM, and is sensitive to most elements in the parts per million range.
An EELS spectrum looks somewhat different than an EDS spectrum (see Figure 2). This graph shows a typical EELS spectrum. The values on the x-axis represent the energies lost by the electrons after they interact with the sample. Notice that there is a large peak at zero electron volts. These are zero loss electrons. These are ballistically transported electrons or elastically scattered electrons that retain their primary energies as they travel through the sample. There is a minor peak between 50 and 100 volts. These are low loss electrons, or electrons that interact with weakly bound outer shell electrons. This includes plasmons or resonance of valence electrons. The larger peaks at higher energies, like the one at 150 electron volts and the other at 330 electron volts, are high loss electrons. These are electrons that interact with inner shell electrons, causing excitation into an unoccupied shell above the Fermi level. The result is characteristic elemental energy loss edges. For example the K and L edges are excited by the 1s and 2s-2p electrons respectively. Sometimes, minor perturbations can be seen on the major peaks. These minor bumps can give the analyst insight into the bonding of the elements in the sample. Each element has a specific energy-loss and near-edge structure, or ELNES, which can be used to determine the valence state and nearest neighbor coordination of the atom analyzed. Bond lengths and coordination of molecular groups can be determined using extended energy loss structures, or EXELFS, which extend beyond the energy-loss edge maxima.
Figure 3 shows an example of an EELS spectrum on a sample with a defect in the gate region of an MOS transistor. Interestingly, this defect showed significant contrast in the FIB, but very little in the TEM image. The engineers used EELS to determine that the anomaly was actually an aluminum or aluminum oxide particle incorporated into the gate region.
Like energy dispersive x-ray spectroscopy, EELS can also yield elemental dot maps. These examples show dot maps that highlight certain elements. The dot maps come from the same field of view. The dot map on the left is a nitrogen map and shows a nitride layer on an integrated circuit, while the dot map on the right is an oxygen map and shows an oxide layer on a circuit. EELS dot maps can have a sensitivity down to the parts per million range, and can provide a spatial sensitivity of 10 nanometers or better.
In summary, EELS is a powerful technique for determining the elemental constituents of defects at the nanometer-scale level. EELS requires significant sample preparation since one performs EELS in the TEM or STEM. As feature sizes shrink further, EELS is one of the few techniques that allow engineers to see potential defects and analyze their composition. This is crucial for problem-solving and corrective action.
One method for reducing the cost of test is to test components in parallel on the same test system. Test engineers commonly use this approach on devices with low pin counts. Many analog and mixed-signal devices fall into this category. Ideally, one should be able to achieve a factor N speedup, where N is the number of devices tested in parallel. Sometimes N is referred to as the number of test sites, or simply number of sites. In reality, one cannot achieve this ideal increase in test efficiency. Factors like program loads and setups for parallel testing cannot be shrunk, so one cannot achieve 100% efficiency in parallel test. Therefore, engineers use a concept called Parallel Test Efficiency, or PTE, to describe the increase from multi-site testing.
The equation for Parallel Testing efficiency is:
where; x is the parallel test efficiency, N is the number of sites, Tm is the multi-site test time, Ts is the single site test time.
We can write this in a different form if we’re interested to determine the multi-site test time.
TM x×TS + N (1 - x)TS, where x×TS is the parallel component and N (1- x)TS is the serial component.
Let’s work an example then. Let’s assume that we have a test configuration for a single site test and a four-site test. Let’s assume the test times are 0.65 seconds for the single site and 0.95 seconds for the four-site test. The parallel test efficiency would then be:
Q: Why are IC test floors so loud?
A: The air conditioning and tester fans create the noise. Automatic Test Equipment to test high performance ICs use a lot of power. These systems need to be able to produce and capture accurate waveforms at high frequencies. This requires specialized circuits that dissipate a lot of power. When you couple this with the fact that a test system might require several hundred of these circuits, and the fact that there might be dozens of testers on a test floor, a lot of heat must be dissipated. A round number for a tester might be 10 watts per channel times 400 channels. Therefore, 20 testers would dissipate 80,000 watts. If the A/C were interrupted on one of these test floors, the temperature would climb 40 °F (22 °C) in a matter of 15 minutes.
Please visit http://www.semitracks.com/courses/processing/wafer-fab-processing.php to learn more about this exciting course!
(Click on each item for details).
Wafer Fab Processing on November 7, 2013 (Thurs.) in San Jose, CA, USA
Advanced Thermal Management and Packaging Materials on November 19-20, 2013 (Tues.-Wed.) in Philadelphia, PA, USA
Semiconductor Reliability on February 11-13, 2014 (Tues.-Thurs.) in San Jose, CA, USA
Failure and Yield Analysis on February 17-20, 2014 (Mon.-Thurs.) in San Jose, CA, USA
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at email@example.com.
To submit questions to the Q&A section, inquire about an article, or suggest a topic you would like to see covered in the next newsletter, please contact Jeremy Henderson by e-mail (firstname.lastname@example.org).
We are always looking for ways to enhance our courses and educational materials.
Home > Newsletters > 2013 October Newsletter