As any news channel will remind you, the world economy has been sliding deeper into recession as a result of easy credit conditions for the past 10 years. The economic downturn is likely to last for quite some time, with any recovery being modest at best. Since semiconductor content pervades nearly all aspects of the economy, the industry rises and falls in much the same way the world economy rises and falls. industry is currently laying off many thousands of people. Some of these people may be your friends; you may even be one of these people. Most of the economic forces are beyond our control. They are beyond the control of your management, and may even be beyond the control of your company’s executive management. What’s an analyst to do?
We can only control our own behavior and actions. Given that we might need to locate a new job at any time, we need to keep our education up to date and prepare ourselves to do failure analysis of any type. In this article, however, I would like to shift the focus on the recession’s impacts on the FA process.
Although many companies tend to scrimp on FA during economic hardship, the reality is that failures still occur and need to be addressed. The FA operation still needs to provide a reasoned, scientific approach to solving problems. Analysts need to resist the urge to “solve problems on the cheap” by skipping steps and reducing data-gathering. Management is likely to put pressure on the FA lab to reduce costs by pumping out more analyses using fewer employees and fewer dollars. It is the job of the lab manager to press back and educate management in the problems associated with doing this. A rushed analysis is more prone to errors. Overworked, tired analysts also generate more errors. When I worked at Honeywell in the 1980s, we did a study to determine if overtime increased the output of the FA lab. The findings were interesting. Overtime increased the output for about two weeks, but after the initial two weeks, the output fell back to the original level. More interestingly, the number of undiscovered and misidentified failures increased substantially. The analysts became tired and irritable, and their work quality suffered as a result. The cost of misidentification or no identification of a failure mechanism greatly exceeds the savings that result from cutting back in the FA lab.
With that said, we need to do our part to cut costs to help our companies survive. In many instances, we can manage by using less expensive tools, researching alternate techniques, taking advantage of commercial labs, and discussing the necessity of an analysis with the customer before starting it. The equipment, techniques, and people may change, but the philosophy and the process should not change. Does FA change in a recession? The answer is emphatically "No and Yes."
This month’s technical tidbit is on transmission line pulse (TLP) testing, an excellent method for characterizing a device’s response to a fast ESD pulse. One can produce a current-voltage characteristic for an input or output pin. This can be useful for determining snapback characteristics and the behavior of a structure in the low-resistance on condition.
This diagram shows the basic elements of a transmission line pulse system. TLP testers use a 50-Ω coaxial cable to form and transmit the pulse. The length of the cable determines the length of the test pulse. Each meter of cable adds roughly 9 ns to the pulse. About 10m of cable is necessary in order to get a 100-ns pulse. A low-resistance relay connects the cable to the DUT through either a resistor, as shown in the diagram above, (referred to as the constant-current method) or an attenuator and low-pass filter (referred to as the constant-impedance method). To measure the voltage across and the current through the DUT during a TLP pulse, a TLP tester uses an oscilloscope with at least a 500-MHz bandwidth. A voltage probe connects between the device's test pin and ground. A current probe measures the current that enters the DUT.
While many TLP testers use constant-current and constant-impedance methods to calculate current, others use time-domain reflectometry. These testers use a delay line and an attenuator following the relay.
The tester measures the amplitude of the current pulse entering the delay line, and then it measures the amplitude of the reflection from the DUT. From the difference in amplitude, the tester can calculate the current and voltage in the DUT. The delay line ensures that the reflected signal won't interfere with measurements on the incident signal.
Regardless of which method you use to calculate current, the TLP tester injects current into a MOS device's drain with the gate and source grounded. If the tester increases the pulse amplitude, failures will begin to occur when the end of the pulse reaches the DUT. By that time, the device will have had to withstand all of the pulse's total energy.
Q: I had a question about multiple contacts. Design software often allows for additional contacts if there is room. Is there any reason not to have multiple contacts? Also, is there any difference between Al and Cu? --Joey
A: Dear Joey: As with many things in the semiconductor industry, it depends. Usually, adding more contacts increases electromigration lifetime. However, the graph below shows a situation where it doesn't. In some cases, you can get a bimodal distribution. You still have early failures because the line, rather than the via, fails. This can be the case with both copper and aluminum. This is usually an issue when the shunt layer sheet resistance exceeds the via resistance. Hope that helps!
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