This article is the conclusion of our series on failure analysis procedures. As we have been discussing over the past several months, sometimes failure analysts can best understand the FA procedure for a component by thinking about the process in terms of the type of failure. This is a flowchart that describes how to analyze a short or a leakage failure at either the wafer or package level. Both flows are very similar, so we will discuss them together.

Figure 1 shows a flowchart that describes how to analyze a short circuit. We begin by examining the device with a curve tracer to check for the short. The pin or bump exhibiting the short should be identifiable from the automatic test equipment (ATE) datalog for the device. If the device has not been tested it should be tested using ATE to confirm the failure. We can also do this directly with the curve tracer, but it can be very time-consuming for a device with many pins, bumps, or bond pads if we’re doing this at the wafer level. The flow now branches if we have a packaged device. If we have a packaged device, we can perform x-ray radiography and scanning acoustic microscopy to look for a wire or bump short, void, crack or some other anomaly. There are other advanced techniques one can try like time domain reflectometry or Superconducting Quantum Interference Device (SQUID) microscopy as well to help localize this type of problem. If we are able to locate a shorted wire, shorted ball, or other obvious anomaly, we can document it and proceed to the report generation. If there is no obvious defect or problem, then the problem most likely lies on the die itself. It makes sense to decapsulate the device to expose the die surface. After decapsulation, one should re-check the pin in question to make sure the short is still present. If the failure is no longer present, then an optical or SEM inspection might be in order at this point to look for anything that might have been missed. If the failure is still present, then we can begin to isolate it on the die. If the package structure is still present, we can use a technique like Liquid Crystal Thermography for a front-side analysis approach, Light Emission, or laser-based techniques like TIVA (Thermally-Induced Voltage Alteration) or OBIRCH (Optical Beam-Induced Resistance Change) to localize the short from both the front or the backside. However, if the package structure is no longer present, then we will need to use a more traditional technique like passive voltage contrast. We then enter a loop where we remove overlying layers to expose the layer of interest, and perform voltage contrast. We can continue in the loop until we identify the failure site or reach the silicon substrate. If we don’t see incorrect contrast, then we can remove the chip layers down to the next metal layer in the node, or down to the upper-most metal layer in the next candidate. We would continue this process down through the backend of the process, or through the interconnect and dielectric layers. Once we see incorrect contrast or the defect itself, we can determine if we need further analysis. This might involve a cross-section or liftout of material. We can then examine the defect with the SEM or TEM as appropriate. If we do not see the defect after removing all of the interconnect and dielectric layers, we can decorate the substrate to highlight potential defects in the silicon. At this point, we can write up our findings in a failure analysis report.

Figure 2 shows a flowchart that describes how to analyze a leakage failure. This flowchart is quite similar to the flowchart we showed in Fig. 1 to describe how to analyze a short circuit failure. Therefore, we will just point out the differences. The main difference in looking for a leakage path as opposed to a short is the magnitude of current involved. A leakage path is likely to have a much lower current than a short. Furthermore, a leakage path may still allow the device to function properly. Therefore, electrical test techniques like IDDQ (Quiescent Power Supply Current) testing become more important. Furthermore, the curve tracer also becomes more important as characterization tool. A leakage path in the package can be quite difficult to detect. Superconducting Quantum Interference Device (SQUID) microscopy is an important technique to help localize this type of problem. Leakage isolation at the die level can also be challenging. Maintaining the package structure becomes more important, since techniques like Passive Voltage Contrast are less effective. If the package structure is still present, we can use techniques like Liquid Crystal Thermography for a front-side analysis approach, Light Emission, or laser-based techniques like TIVA (Thermally-Induced Voltage Alteration) or OBIRCH (Optical Beam-Induced Resistance Change) to localize the leakage path from both the front or the backside. Analysts use passive voltage contrast to identify opens and shorts. If we don’t see incorrect contrast, then we can remove the chip layers down to the next metal layer in the node, or down to the upper-most metal layer in the next candidate. This may require some manual probing with probes in the SEM or an Atomic Force Probe system. We would continue this process down through the backend of the process, or through the interconnect and dielectric layers. Once we see incorrect contrast, identify the defective transistor, or interconnect segment, or the defect itself, we can determine if we need further analysis. This might involve a cross-section or liftout of material. We can then examine the defect with the SEM or TEM as appropriate. If we do not see the defect after removing all of the interconnect and dielectric layers, we can decorate the substrate to highlight potential defects in the silicon. At this point, we can write up our findings in a failure analysis report.

While FA becomes more challenging as we go to smaller and smaller feature sizes, there are some standard flows that work well. These five FA flows we have discussed in this and previous articles can help the analyst structure their work in a logic manner to increase the chances for success. If you would like to learn more about FA processes, we would encourage you to sign up for access to our Online Training System. The system contains a number of presentations that talk not only about this topic, but also other procedures used in failure analysis. The link to learn more is shown here: http://www.semitracks.com/online-training/

This Tidbit will focus on demonstrating a method to solve for an unknown voltage in a simple circuit like this one (see Figure 1 below) using Matlab. It might be useful to know what the voltage is between the two, four and eight ohm resistors. This is not very difficult to find by hand, but it is even easier with Matlab, and you can set it up so that you can test various voltages quickly.

Decide on a reference node, which is usually the ground. Label all remaining nodes. You will need to apply Kirchoff's current law to each node not connected to the voltage sources. Kirchoff’s Current Law states that the sum of the input currents into a certain point must equal the sum of the output current. In our example, both current 1 and current 2 feed into current 3, so the sum of current 1 and current 2 must be equal to current 3. Take each current 'I' and split it up according to Ohm’s law. Because V1 feeds directly into v sub a, V1 is equal in voltage to v sub a. The same is true of V2 and v sub b. Because of this, we can replace v sub a and v sub b in our equations with V1 and V2. Now that we’ve minimized the amount of unknowns in the equations, we can solve with Matlab. This equation will be easy to set up, due to the fact there will only be one unknown, V sub b.

Here’s an example of a way this might be coded in Matlab (see Figure 2 below). We’ll provide a few notes on the coding for people who might be a little rusty with Matlab. 'syms vb' on line 3 defines v sub b as a symbolic variable with no set value. Line 4 sets the equation you entered equal to the variable 'equation'. The 'sym()' command takes the string inside of it and recognizes it as a symbolic equation instead of the string of numbers it usually expects. Failure to use 'syms' or 'sym()' will cause errors, because it usually needs variables like vb to be defined in a solid, numerical way. You could solve the equation for any defined variable by changing the text that is currently 'vb' in line 8 to the variable you want to solve for. Line 9 solves the equation in terms of vb. The solve (x,y) function takes the equation x and solves in terms of y. Line 10 displays the newly arranged equation when you run the program. It is understood that the equation is equal to 'vb', so when it displays the equation, instead of being in the format 'y = mx -b', it’ll be in the format 'mx-b'. Lines 12 through 16 set each variable in the equation equal to a numerical value. These values are from the initial circuit. Line 17 takes the rearranged equation and evaluates it using the numerical values. Line 18 displays the value of the equation. Since the equation is equal to 'vb', this is the unknown voltage 'vb' that we were trying to solve for.

This completes the generation of the function. If you run it exactly like this, the output will show you the initial equation, the rearranged equation, and the answer. You can hide the first two by adding semicolons to the ends of lines 5 and 10.

Here’s the code, if you’d like to copy and paste it into Matlab.

function voltagesolver

clc

syms vb

equation=sym('(vb/r3)=(((v2-vb)/r2)+((v1-vb)/r1))');

disp(equation)

%A list of Variables that could be solved for:'vb',

%'v1','v2','r1','r2','r3'

var='vb';

rearrangedequation=solve(equation,var);

disp(rearrangedequation)

%values for other variables

r1 = 2;

r2 = 4;

r3 = 8;

v1 = 32;

v2 = 20;

answer = eval(rearrangedequation);

disp(answer)

end

**Q: Today, you see a lot more equipment using Dry Pumps. Why is this?**

**A:** This is primarily due to the fact that oil-based pumps suffer from a phenomenon known as backstreaming. Oil vapor can be sucked back into the system chamber. In a wafer fabrication tool, this can lead to contamination on the wafer surface, which can interfere with processing and limit the yield. In an analytical tool like a scanning electron microscope, the oil vapor on the surface can be carbonized or polymerized by the electron beam, creating a thin layer that interferes with imaging. Furthermore, this material is difficult to completely remove. The best way to avoid these problems is to use a dry pump instead.

Please visit http://www.semitracks.com/courses/photovoltaics/thin-film-photovoltaics-reliability.php to learn more about this exciting course!

(Click on each item for details).

Failure and Yield Analysis on March 18-21, 2013 (Mon.-Thurs.) in San Jose, CA, USA

Wafer Fab Processing on March 26, 2013 (Tues.) in San Jose, CA, USA

Semiconductor Reliability on April 3-5, 2013 (Wed.-Fri.) in San Jose, CA, USA

Advanced Thermal Management and Packaging Materials on April 22-23, 2013 (Mon.-Tues.) in Philadelphia, PA, USA

If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at info@semitracks.com.

To submit questions to the Q&A section, inquire about an article, or suggest a topic you would like to see covered in the next newsletter, please contact Jeremy Henderson by e-mail (jeremy.henderson@semitracks.com).

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