Feature Article - What’s Inside an FPGA? - By Christopher Henderson

Increasingly, Field Programmable Gate Arrays (FPGAs) are replacing custom ASICs. Today’s FPGAs can incorporate large amounts of logic, memory, and other specific functions, such as processor cores, high speed signaling, and standard interface protocols. The image at the head of this article shows the chip layout for the Xilinx Vertex II, a common FPGA. We will use this FPGA to discuss some of the basic features of these powerful chips.

Opposite is the basic block layout for the Xilinx Virtex II Pro FPGA. The majority of the die is populated with configurable logic blocks for implementing functionality. Some blocks, like the IBM Power PC 405 series core, can be reserved for drop-in processing elements. The channels between the logic blocks are configured as block select RAM multipliers; these blocks can perform 18-bit by 18-bit multiplication operations. On the periphery, the blocks can be configured with digital clock managers, multi-gigabit serial transceivers, and highly versatile input-output blocks. The digital clock managers can reduce clock skew problems across the chip, generate a wide range of clock frequencies, perform clock multiplication or division, and provide phase shifting. The multi-gigabit serial transceivers provide high frequency serial communications on and off the FPGA. Finally, the input/output logic blocks provide for a multitude of voltage and drive levels, as well as newer concepts like low voltage differential signaling.

As shown in the diagram on the following page, a Virtex II configurable logic block contains four similar slices that are split into two columns of two slices each. Each column contains two independent carry logic chains and one common shift chain. Every slice is tied to a switch matrix that allows access from the general routing matrix. Each slice has an upper half and a lower half. Each half contains a dual port shift register that can be configured as a lookup table, 16 bits of random access memory, or a 16-bit variable tap shift register element. Each half also contains a register/latch function to implement sequential logic and the logic to permit integration of the two halves.

The Xilinx Virtex II cell architecture, shown in detail below, represents an advanced FPGA cell design. In the case of the Virtex II, a complementary slice is not shown. The basic function generator is implemented as a four-input lookup table, labeled here as block G. This results in a propagation delay that is independent of the function that one implements. The function can exit the cell block through the GYMUX, go to the dedicated exclusive or gate, input the carry logic multiplexer, feed the d input on the register, or feed the logic from the bottom slice to implement more complex logical functions. The register can be configured either as an edge- triggered flip flop or as a level sensitive latch.

Each slice has clock, clock enable, set, and reset signals to provide additional control. The set function can be configured to be either synchronous or asynchronous. The dual port shift register can also be configured as memory. One can implement a sixteen by one bit synchronous random access memory resource. Since two slices can work in tandem, one can create a variety of memory blocks ranging from single port sixteen by eight blocks to a dual port sixty-four by one block.