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Design for Reliability

Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing and modeling failure mechanisms, and then determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. The product lifecycle for many components has become so short that there are limited opportunities to impact the overall reliability of the device, whether that be testing at the package level or even the wafer level. While reliability levels are at an all-time high in the industry, rapid changes may quickly cause reliability to deteriorate. This requires that one put thought and effort into the reliability of a component upfront, during the design phase. The question is how to do this properly. The industry needs competent engineers and scientists to help solve these problems. Design for Reliability is a 1-day course that offers detailed instruction on a variety of subjects pertaining to designing in reliability. This course is designed for every manager, engineer, and technician concerned with reliability in the semiconductor field, designing semiconductor components, or supplying tools to the industry.

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Cost

$300

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Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.

Please email the printable registration form for public courses to us at the email address on the form to complete your order.

Additional Information

If you have any questions concerning this course, please contact us at info@semitracks.com.

Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

Participants will learn to develop the skills to determine what failure mechanisms might occur, and how to develop models for them, understand their impact at the circuit, block, and IC level, and minimize their impact in the product. This skill-building series is divided into three segments:

  1. Fundamentals of Reliability Physics and Accelerated Testing. Participants will learn the fundamentals of various failure mechanisms and the testing used to accelerate those mechanisms.
  2. Design-In Reliability Issues. Participants will learn how the major failure mechanisms manifest themselves at the circuit and chip level. These include: time-dependent dielectric breakdown, hot carrier degradation, electromigration, stress-induced voiding, moisture, corrosion, contamination, and thermomechanical effects. Participants will learn the process for converting test structure results into circuit level behaviors.
  3. Mission Profiles. Participants will learn the conversion of transient use-conditions into static equivalents for Design Rule generation and verification.

Course Objectives

  1. This course will provide participants with an in-depth understanding of the failure mechanisms, test structures, equipment, and testing methods used to achieve today's high reliability components.
  2. Participants will be able to identify basic test structures and how they are used to help quantify reliability on semiconductor devices.
  3. Participants will be able to interpret test structure data and make inferences from that data.
  4. This course will identify the major failure mechanisms, explain how they are observed, and how they are modeled at the circuit level.
  5. Participants will learn to convert dynamic condition test data into a static model that can be used in the design environment for design rule checking and layout.
  6. Participants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.
  7. Participants will be able to identify appropriate software tools to purchase when starting or expanding their design operations.

Course Outline

DAY 1

  1. Device-Parameter Degradation
  2. Degradation Modeling
  3. Time-to-Failure Modeling
  4. Time-to-Failure Statistics
    • Normal
    • LogNormal
    • Exponential
    • Weibull
  5. Accelerated Degradation
  6. Acceleration Factor
    • Arrhenius
    • Eyring (Black's Model, Peck's Model, others)
    • Power Law (Coffin-Manson)
  7. Six-Sigma Approach to Designs
  8. Design-In Reliability Issues
    • Electromigration
    • Stress Migration
    • Time-Dependent Dielectric Breakdown
    • Hot Carrier Injection
    • Negative Bias Temperature Instability
    • Plasma Damage Issues
    • Thermal Cycling Issues
    • Energy Density Issues
  9. Mission Profiles
    • Understanding Product Mission Profiles
    • Conversion of Dynamic Voltage Conditions into Static Equivalents for Design Rule Generation/Verification
    • Conversion of Dynamic Power/Temperature Conditions into Static Equivalents for Design Rule Generation/Verification

Instructional Strategy

Our courses are dynamic. We use a combination of instruction by lecture, problem solving, and question/answer sessions to give you the tools you need to excel in semiconductor reliability design. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. The course notes offer hundreds of pages of reference material that the participants can apply during their daily activities.

Our instructors are internationally recognized experts. Our instructors have years of current and relevant experience in their fields. They're focused on answering your questions and teaching you what you need to know.

Instructor Profile

Christopher Henderson, President of Semitracks

Christopher Henderson

Christopher Henderson received his B.S. in Physics from the New Mexico Institute of Mining and Technology and his M.S.E.E. from the University of New Mexico. Chris is the President and one of the founders of Semitracks Inc., a United States-based company that provides education and semiconductor training to the electronics industry.

From 1988 to 2004, Chris worked at Sandia National Laboratories, where he was a Principal Member of Technical Staff in the Failure Analysis Department and Microsystems Partnerships Department. His job responsibilities have included failure and yield analysis of components fabricated at Sandia's Microelectronics Development Laboratory, research into the electrical behavior of defects, and consulting on microelectronics issues for the DoD. He has published over 20 papers at various conferences in semiconductor processing, reliability, failure analysis, and test. He has received two R&D 100 awards and two best paper awards. Prior to working at Sandia, Chris worked for Honeywell, BF Goodrich Aerospace, and Intel. Chris is a member of IEEE and EDFAS (the Electron Device Failure Analysis Society).

At Semitracks, Chris teaches courses on failure and yield analysis, semiconductor reliability, and other aspects of semiconductor technology.