Semiconductor packaging developments continue to proceed at an incredible pace. A relatively new packaging technology making inroads in electronic systems is wafer level chip scale packaging (WLCSP). In WLCSP, the bonding, testing, and bumping is performed at the wafer level. This can lead to faster, more power-efficient products, and products compatible with smaller form factors. WLCSP is a marked departure from conventional packaging techniques, so the tools, technologies, and processes are quite different. This has created a number of challenges related to the packaging of these components. Wafer Level Chip Scale Packaging Technology is a 2-day course that offers detailed instruction on the technology issues associated with today's WLCSP semiconductor packages. We place special emphasis on current issues like conductive adhesives, gold, copper, nickel-gold materials, stud bumping, and through-silicon vias (TSVs). This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.
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Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.
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By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.
Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments:
By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor packaging and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field.
More than twenty years experience in electronics and manufacturing with duties including, President, Chief Technologist, and Director of Engineering focusing on new product, new process, and new market development in the area of Integrated Circuit (IC) packaging and test.
Part of the core start-up team that established the world leading IC packaging factories at STATS/Chippac in Singapore, Amkor Electronics in the Philippines, and Amkor/Anam Electronics in Korea.
Direct hands on development of all types of IC packaging technologies including wafer RDL and bumping, WLCSP, flip chip packaging, LGA/BGA large die stack packages with up to 16 die, and multiple die stack leadframe packages.
Wrote and awarded numerous U.S., Singapore, and other international patents and inventions relating to IC packaging. Published and presented a variety of technical papers worldwide and recognized expert in packaging worldwide. Received B.S.M.E. degree from the University of Central Florida in Mechanical Engineering and began working the same year in electronics packaging for Northern Telecom.