System Maintenance occurs every Friday.

IC Packaging Design and Modeling

IC packaging complexity levels are rising year-by-year in lock step with process advances and electrical performance enhancements. Single die packages with leads have given way to multi-chip area array packages, stacked die packages, and stacked packages. Pin-counts have increased from a few handfuls to thousands. Space constraints for consumer products have required shrinking some packages to barely larger than the chip volume, and high-performance applications have required ever increasing levels of power dissipation and higher frequency operation. Pin count increases alone driven by wide I/O have driven substrate technologies to include upwards of 20 or 30 interconnect layers. Higher integration levels in automotive applications have motivated higher reliability requirements. At the same time, time-to-market and cost reduction requirements have forced an ever-accelerating product development pace where missing a product launch can spell a company’s doom. Trial and error iteration won’t work in today’s industry.

The only way to meet the interrelated demands of complexity, performance, time-to-market, and reliability is through appropriate package design processes and modeling. This two-day class will cover fundamental issues in package design, including the need for appropriate risk analysis, up-front design rules, early look-ahead, and modeling coupled with verification. Participants will learn the fundamentals of thermal and electrical analysis for performance characterization. Compact models that enable transferring phenomenological behavior between die, package, and system level models will be described. Mechanical analysis examples applied to a wide range of reliability issues will be emphasized with a focus on solving issues in advance. Participants will learn the critical factors that must be implemented to ensure the success of their package designs and products.

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Course Dates | Location

September 18-21, 2023 | Online Webinar

8:00 AM to 12:00 Noon PDT



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Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

Participants will learn critical skills required to design a fully functioning IC package that meets competing requirements. This skill-building series is divided into four segments:

  1. Packaging Design Overview. Participants learn the fundamentals of packaging design. They learn why modeling has become critical to today’s semiconductor packaging and how important co-design from the chip level through the system level is to product performance.
  2. Mechanical Simulations. Participants learn the fundamentals of displacement, strain, stress, and energy and how to interpret the stresses that can be calculated. They learn how to apply fracture mechanics to a problem.
  3. Thermal Simulations. Participants learn heat transfer modeling. They also learn about steady-state and transient thermal modeling. Reasons for and the topology of industry standard and compact thermal models will be described.
  4. Modeling Semiconductor Packages. Participants learn about the software used for modeling a variety of aspects of semiconductor packaging. They see many examples of current modeling tools used by package design experts.

Course Objectives

  1. Application spaces for each package family will be covered, including the primary constraints and care-abouts for the product spaces.
  2. A thorough listing of interrelated factors will be detailed to enable participants to understand what factors throughout the entire package design chain must be considered when making modifications to one or more package constituents.
  3. Mechanical modeling will be highlighted as a tool to be used to develop a parametric understanding stress impacts. For example, if an underfill modulus is changed, what happens to the stresses on the circuits under the bumps, on the die interface, in the underfill etc.
  4. Participants will know the types of stress analyses that should be performed for each package question, as well as the inputs and verification that is required to ensure the model is producing real answers, not just numbers.
  5. Thermal and electrical modeling techniques needed to verify a package’s performance well before tooling is committed will be described.
  6. Participants will learn from real examples how best to utilize package design tools and will learn their strengths and weaknesses.
  7. Participants will see examples of package design rules that, when incorporated in design manuals, enable robust reliable package design. Participants will learn how to develop package design rules for their own products.
  8. Knowledge gained from the class will improve time-to-market for participants by helping them avoid costly qualification failures.

Course Outline

Day 1

  1. Assembly & Packaging Processes
    1. Material Selection
    2. Typical Assembly Process Flows
    3. Package Types & Evolution
    4. Simulation Tools & Applications
    5. Risk Evaluation & Risk Mitigation
  2. Design for Manufacturability (DfM)
    1. Solid Mechanics
    2. Assembly-Induced Stress
    3. Package Warpage & Coplanarity
    4. Die Bonding, Wire Bonding, & Microbump Bonding
    5. Mold Flow Modeling and Correlations
  3. Design for Reliability (DfR)
    1. Chip-to-Package Interaction (CPI)
    2. Interfacial Delamination & Adhesion
    3. Solder Joint Reliability (SJR)

Day 2

  1. Design for Performance
    1. Heat Transfer
    2. Package Thermal Resistance
    3. Steady State & Transient Thermal Behavior
    4. Power Distribution and Noise
    5. Compact Models
    6. Drop Testing & Simulation
  2. Advanced Packaging Examples
    1. Multichip Packages
    2. Stacked Packages
    3. Wafer Level Packaging
    4. 3D Packaging
    5. Through Silicon Via (TSV) Interconnects

Instructor Profile

Steve Groothuis

Steve Groothuis

Steve Groothuis received a Bachelor's in Physics (1983) from Michigan State University and Masters in Physics (1991) from the University of Texas. He began work in the Central Packaging Group, Texas Instruments in Dallas in 1983 as a Group Member of the Technical Staff performing semiconductor package development, design, testing, and simulation. Prior to leaving TI, he managed the engineering staff in TI's Advanced Semiconductor Packaging Lab. In 1997, he was a Multiphysics Industry Specialist for ANSYS Inc. defining Computer-Aided Engineering simulation software market plans, strategic accounts management, Electronics Packaging, MEMS Device Simulation initiatives, and product development for the Electronics Industry. From 2000-2008, he was with Micron Technology in positions from Senior Package Engineer in the Assembly and Packaging Department to Technology CAD, and Analysis Manager in the Process RD Department at Micron Technology. His responsibilities included device and process simulations for new cell designs, supporting most aspects of semiconductor package simulations, and new technology assessments.

Currently, Mr. Groothuis is a Principal Consulting Engineer with SimuTech Group Inc. He is actively involved in developing and winning new business opportunities for Finite Element Analysis (FEA) and Computational Fluid Dynamics (CFD) consulting projects. His efforts are focused on vertical markets such as Microelectronics, Semiconductor Packaging, Wafer Fabrication, NEMS/MEMS, Nanotechnology, Solar Energy, Wind Energy, and Consumer Electronics.

He has published over 30 papers at various conferences in semiconductor packaging, reliability, and numerical analysis. Mr. Groothuis is a Senior Member of the IEEE and has participated in ASME and JEDEC standards committees.