IC packaging complexity levels are rising year-by-year in lock step with process advances and electrical performance enhancements. Single die packages with leads have given way to multi-chip area array packages, stacked die packages, and stacked packages. Pin-counts have increased from a few handfuls to thousands. Space constraints for consumer products have required shrinking some packages to barely larger than the chip volume, and high-performance applications have required ever increasing levels of power dissipation and higher frequency operation. Pin count increases alone driven by wide I/O have driven substrate technologies to include upwards of 20 or 30 interconnect layers. Higher integration levels in automotive applications have motivated higher reliability requirements. At the same time, time-to-market and cost reduction requirements have forced an ever-accelerating product development pace where missing a product launch can spell a company’s doom. Trial and error iteration won’t work in today’s industry.
The only way to meet the interrelated demands of complexity, performance, time-to-market, and reliability is through appropriate package design processes and modeling. This two-day class will cover fundamental issues in package design, including the need for appropriate risk analysis, up-front design rules, early look-ahead, and modeling coupled with verification. Participants will learn the fundamentals of thermal and electrical analysis for performance characterization. Compact models that enable transferring phenomenological behavior between die, package, and system level models will be described. Mechanical analysis examples applied to a wide range of reliability issues will be emphasized with a focus on solving issues in advance. Participants will learn the critical factors that must be implemented to ensure the success of their package designs and products.
September 18-21, 2023 | Online Webinar
8:00 AM to 12:00 Noon PDT
$600
Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.
Please email the printable registration form for public courses to us at the email address on the form to complete your order.
If you have any questions concerning this course, please contact us at info@semitracks.com.
If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.
Participants will learn critical skills required to design a fully functioning IC package that meets competing requirements. This skill-building series is divided into four segments:
Darvin R. Edwards received the B.S. degree in Physics from Arizona State University, Tempe, AZ, in 1980 and joined Texas Instruments soon after. Initially at TI, he developed integrated test structures such as strain gauges, moisture sensors, thermal sensors, and structures to determine the impact of package stresses on IC thin film layers. He developed a set of IC design rules for packaging that has been continuously updated and is still in use today. He then worked to build TI’s competence in thermal characterization and thermal management. He wrote a thermal characterization modeling program that was used within TI from 1993 through 2004 and built TI's thermal labs. With JEDEC, he wrote the thermal test board standards.
Elected TI Fellow in 1999, he was manager of the Advanced Package Modeling and Characterization group from 1997 through 2012. His modeling team was responsible for thermal, electrical, and stress analysis for a wide range of product families, as well as ensuring reliability, successful qualification and introduction of products to the market. Packages and technologies he has helped develop include TSV, POP, Cu Pillar, Stacked Die, MCM, FC-BGA, PBGA, QFN, CSP, WLCSP, QFP, LOC, multi-die QFP, and SOICs.
In 2013, Darvin took responsibility for Analog Chip/Package Codesign, developing innovative test structures and reliability design guidelines for TI’s new analog process nodes, including those of high voltage components. Additionally, he created and codified a risk assessment process that was implemented worldwide for TI’s new package development projects. During his career at TI, Darvin also managed at various times advanced package FA technique development, adhesion characterization development, and Sun Flip-Chip microprocessor package development.
After retiring from TI in late 2013, Darvin formed Edwards’ Enterprise Consulting LLC which focuses on bringing expert insights to IC package reliability, failure analysis, and thermal management issues. He is an active professional development instructor for the Electronic Components and Technology Conference, has taught courses for both Pico Tech Resources and Semitracks on topics such as Package Design, Package Reliability, Package Materials, and Surface Mount Technologies. He has regularly served as an expert witness in patent litigations and has spoken at many universities to encourage students to pursue careers in IC Packaging.
Darvin is a two-time past chair of the SRC GRC Interconnect and Packaging Sciences’ Science Area Coordinating Committee, and was TI’s IPS SAC and TAB representative for eight years. He served as a liaison on many SRC research projects, working regularly with various universities and research institutes to coordinate TI’s external packaging research interests.
Professional activities have included over 35 years of service on the Applied Reliability program selection committee of the ECTC, which he has chaired numerous times. Darvin also authored five JEDEC standards including the PCB specifications for low and high effective thermal conductivity test cards. He has contributed to both the ITRS and iNEMI roadmaps. He has authored and co-authored over 60 papers and articles in the field of IC packaging, including two best paper awards and an Intel best student paper award, has written two book chapters, and has given multiple keynote addresses, lectures, tutorials, and short courses. He holds 23 US patents. Darvin is an IEEE Senior Member and is serving his fourth term on the CPMT Board of Governors.