Microelectronic and now nanoelectronic manufacturing have become increasingly challenging with higher density packaging, transistor counts into the billions, dimensional scaling, new materials, and three-dimensional packaging. Yield, reliability, and quality engineering are increasingly critical to quick and cost-effective product introduction and client satisfaction.
Finding, understanding, and correcting defects are all critical to improving yield, reliability, and quality. Numerous defect mechanisms can cause failure and a large number of complicated techniques are required to localize, identify, and characterize them. This course provides an overview of microelectronic test, electrical faults and failures, physical defects, fault isolation, and failure analysis techniques for simple and advanced ICs and microelectronic packages. The theory and application of testing, characterization, and analytical tools, techniques, and instruments will be covered along with a wide variety of defect types and examples.
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Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.
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This course will provide attendees with a broad overview of defects, test, diagnosis, failure analysis, and materials characterization as well as the relevant theory and application of numerous analytical techniques and methods. Upon completion students will be able to understand the basic operating principles, use, and limitations of all common methods for analyzing manufacturing yield, reliability, and quality failures.
Mr. David Vallett is a Failure Analysis manager in the Worldwide Analytical Services Technology Quality organization with IBM Systems & Technology Group in Burlington, VT, USA. He has over 30 years experience in CMOS characterization and failure analysis and holds the BS degree in electrical engineering from the University at Buffalo, New York, USA.
He presently manages a department responsible for technology qualification failure analysis, fault isolation, and advanced packaging failure analysis having capabilities in all facets of IC physical failure analysis, electrical and physical fault isolation, depackaging and silicon micromachining, nanoprobing, and X-ray tomography.
Mr. Vallett is widely published in the field with five best-paper awards and has given a number of lectures on analytical technology challenges in both micro and nanoelectronics. He holds fifteen US patents and shared in IBM's Outstanding Technical Achievement award for his contributions to picosecond imaging circuit analysis (PICA) using time-resolved photon emission microscopy.
He is a senior member of the IEEE, a member of the Electronic Device Failure Analysis Society board of directors, and belongs to Tau Beta Pi - the National Engineering Honor Society. He is a past chair of the International SEMATECH Product Analysis Forum and was selected as the 2008 General Chair for ISTFA - the International Symposium for Testing and Failure Analysis.