Notes

We make the slide notes available for several of the courses we teach. When you order the course notes, you also get a CD-ROM copy for quick computer reference. See below for available slide notes.

IC Packaging Design and Modeling

Semitracks, Inc. has assembled a course on IC Packaging Design and Modeling which provides an overview of the packaging design process. The course covers current packaging technologies, including chip scale packaging, Ball Grid Array technology, and other current concepts. This class focuses on techniques and the importance of thermal and mechanical simulations. Discussions and examples will concentrate on thermal performance simulations, assembly & packaging stresses, package reliability (including solder joint fatigue simulation), and interactions between chip and package. In addition, a special section will be examples of successful wafer level simulations.

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IC Packaging Design and Modeling
Course Notes

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$100

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IC Packaging Technology and Challenges

Semitracks, Inc. has put together a course which will provide an overview of the current business climate, anticipated trends, and the associated impact on assembly/packaging roadmaps. There will be an in-depth discussion of both high-end CPU roadmaps plus the roadmaps to address the multitude of communications and network devices that are driving the digital revolution. The course will generically address typical assembly flows and cost implications for both wafer fabrication and assembly, with special focus on what the low-cost alternatives will be in both camps.

Based on the technical reliability issues that the packaging roadmaps drive, such as thin film delamination/cracking, bump cracks, via delamination/cracking, thermal interface degradation, heat sink retention, and socketing issues, there will be a review of commonly used failure analysis tools and techniques appropriate to each failure mechanism. Thus, state-of-the-art, non-destructive imaging tools of acoustics, x-ray, scanning SQUID microscopy, and terahertz imaging will be reviewed with respect to advantages, limitations, and likely evolution to next generation. Other techniques that will be discussed are time domain reflectometry (TDR), adhesion testing, thin film materials characterization, and disassembly techniques to allow fault isolation and failure analysis. The course will cover the impact of next-generation technologies such as Cu, ultra low-k dielectrics, 300mm wafer fabrication, wafer scale packaging, embedded passives, chip on board, and modular integration. Finally, the course will hint at the future, with a focus on Nanotechnology, Connectintelligence, and the currently ill thought-out arena of what packaging/assembly means for this era of molecular devices.

This course is recommended for engineers and scientists involved in setting the direction for adapting to the rapidly exploding arena of assembly/packaging in the digital revolution. This course will also be especially useful to engineers and scientists actively engaged in performing risk assessments on packaging technologies, performing fault isolation and failure analysis, and performing stressing to achieve reliability certification of such technologies.

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IC Packaging Technology and Challenges
Course Notes

Cost

$100

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Please fax the printable purchasing form for books, manuals and notes to us at 1-866-205-0713 to complete your order.

Reliability and Characterization Challenges

The continued scaling of gate dielectric thickness has resulted in increased leakage current and shrinking reliability margins. Designers must balance circuit performance with device reliability. The introduction of high-k dielectric materials to reduce gate leakage current presents significant challenges for electrical and reliability characterization. Bulk trapping complicates electrical measurements and wear-out mechanisms are not yet understood. An overview of thin gate oxide reliability will be presented and issues relating to high-k gate oxide reliability will be discussed.

The scaling of transistors exacerbates hot carrier effects. One particularly difficult challenge is overcoming the effects of Negative Bias Temperature Instability (NBTI) and, more recently, Positive Bias Temperature Instability (PBTI). Both NBTI and PBTI can degrade the performance of the p-channel transistor. Boron penetration from the polysilicon gate strongly affects NBTI. Both are also difficult to combat through standard processing techniques.

To improve IC performance, copper metallization and Low-K dielectrics are routinely used in advanced processes. Copper metallization exhibits different electromigration, stress voiding, and corrosion behavior than traditional aluminum-based interconnect systems. The mechanical, thermal, and electrical issues due to copper and its integration with Low-K dielectrics will be discussed. Low-K dielectrics exhibit inferior thermal, mechanical, and dielectric breakdown characteristics compared to traditional silicon dioxide and silicon nitride-based materials.

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Reliability and Characterization Challenges
Course Notes (2007)

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$100

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Wafer Fab Processing

This intensive 4-day course offers a comprehensive examination of the wafer fab processes used to manufacture state-of-the-art microchips. Topics include semiconductor devices and ICs, silicon crystal growth and crystal defects, ion implantation, thermal processing, contamination control, wafer cleaning, LPCVD, PECVD, PVD, CMP, microlithography, etch, multilevel interconnect technology, and manufacturing technology. Process integration will be illustrated using a basic CMOS process flow.

The course is designed primarily for process engineers and process technicians. The emphasis is on understanding how each individual process step works, and understanding the key process control variables for each step. The functional design of the process tools is also discussed, as are process characterization, monitoring, and control.

Engineers new to semiconductor manufacturing will gain a solid, broad understanding of the entire wafer fab process. Engineers experienced in one or more functional areas of wafer fab will benefit from a thorough understanding of processes in other areas, as well as a better appreciation of process interactions.

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Wafer Fab Processing
Course Notes

Cost

$100

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Pay Via Purchase Order/Check

Please fax the printable purchasing form for books, manuals and notes to us at 1-866-205-0713 to complete your order.