Online Training Overview

Welcome to Semitracks' Online Training and Learning Management System

What is Semitracks' Online Training?

Semitracks' Online Training offers Presentations (powered by Articulate), Documentation (Adobe PDF and Microsoft Excel) and Videos (Adobe Flash) as they relate to variety of topics found in today's Semiconductor Industries. These topics are broken down by high level subjects like Failure Analysis, Reliability, Test, and many more; then further broken down into sub-sections dealing with more specific information on a topic.

New to Semitracks' Online Training?

If you are new to Semitracks' Online Training System, please take a few minutes to make sure you have all the necessary ”System Requirements”, and watch the ”How to Navigate our System” presentation, located on the left-hand side of this page.

System Requirements

  • Browser: Microsoft Internet Explorer, Apple Safari, Mozilla Firefox, Google Chrome or Opera.
  • Adobe: Adobe Flash Player ActiveX 10 or higher (for Internet Explorer) or Adobe Flash Player Plug-in 10 or higher (for Safari, Firefox, Chrome and Opera) and Adobe Reader.
  • Audio-Listening Capabilities: Speakers, Headphones, et cetera.
  • Internet Connection Speed: At least 256 kbps (DSL, Cable, T1, et cetera) or faster is recommended.
  • Disable Pop-up Blockers: All of the presentations and videos on this site open in new windows, which requires pop-up blockers to be disabled.

Questions or Comments?

If you have any questions, comments, or suggestions for improvements please email us at: info@semitracks.com.


Legal Notices

This publication may NOT be reproduced (in part or whole), transmitted (in any form), transcribed, stored in a retrieval system, translated into any language or computer language in any form or by any means: electronic, mechanical, magnetic, optical, chemical, manual or otherwise, or distributed to third parties without the prior written permission of Semitracks, Inc.

Semitracks, Inc. makes no representations or warranties with respect to the contents hereof and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. Furthermore, Semitracks, Inc. reserves the right to revise this publication, and to make changes from time to time in the content hereof without obligation of Semitracks, Inc. to notify any person of such revision or changes.

Semitracks, Inc. and other Semitracks products and services mentioned herein as well as their respective logos are trademarks or registered trademarks (™) of Semitracks, Inc. in the United States and other countries.

The following are trademarks or registered trademarks of their respective companies or organizations: Microsoft, Internet Explorer / Microsoft Corporation; Apple, Safari / Apple, Inc.; Mozilla, Firefox, / Mozilla Foundation; Google Chrome / Google, Inc.; Opera / Opera Software ASA; Adobe, Flash Active X and Plug-ins, Reader / Adobe Systems Incorporated. All other brand or product names are trademarks or registered trademarks of their respective companies.

Presentations

How To Navigate Our System

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Terms and Definitions

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Acronyms A-C

Acronyms D-G

Acronyms H-K

Acronyms L-N

Acronyms O-Q

Acronyms R-S

Acronyms T-Z

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Semiconductor Technology Overview

This course provides an overview of the Semiconductor Technology manufacturing process. We divide this course into three sections: processing, packaging and testing. The processing section covers wafer fab processing techniques at a high level. These are the basic tools and techniques used to grow, etch, deposit, and pattern the thin films on a semiconductor or integrated circuit chip. For more detailed information on wafer fab processing techniques, please visit the Processing and Process Integration Classrooms located nearby in this system. The packaging section covers at a high level the basic techniques to package a semiconductor component into a form that can be used in an electronic system. These techniques including wire bonding, die attach, solder ball attach, molding, and so on. We also discuss the packaging design process and the various types of packages. For more detailed information on packaging techniques, please visit the Packaging Design and Packaging Technology Classrooms located nearby in this system. The testing section covers general information on how to test components. It includes an overview of the testing process and materials on various test techniques and design techniques like Scan-Based Testing. For more detailed information on testing techniques, please visit the Test Classroom located nearby in this system.

Processing

Introduction

Fabrication of semiconductors and integrated circuits (ICs) is arguably one of the most advanced manufacturing processes ever developed. A state-of-the-art IC requires a ultra clean environment, ultra pure chemicals and gases, highly sophisticated fabrication tools, and a team with extensive knowledge of chemical engineering, semiconductor physics, modeling, and logistics management. The materials in this section cover the main disciplines or steps used in semiconductor fabrication. They include:

  • Growth and preparation of the starting material (Si, GaAs, or other semiconductor materials)
  • Diffusion
  • Oxidation
  • Cleaning
  • Ion Implantation
  • Lithography
  • Chemical Vapor Deposition
  • Physical Vapor Deposition
  • Chemical Mechanical Planarization

Please click on the topics to the left to begin learning about this fascinating process.

Presentations

Starting Material - Bulk Silicon Process

This section covers the basics of silicon crystal structure, defects, the growth process, sawing, and wafer identification.

Wafer Specifications and Defects

Silicon on Insulator Process

Epitaxial Growth Process

Deposition

This section covers physical vapor deposition and chemical vapor deposition techniques.

Oxidation

This section covers wet and dry oxidation. We cover oxidation models as well as concentration effects.

Diffusion

This section covers the diffusion process. We discuss the physics of diffusion, dopant species, electrical, and concentration effects.

Dry Etching Processes

This section covers reactive ion etch processes for removing materials from a semiconductor device.

Wet Etching Processes

This section covers wet etch processes for removing materials from a semiconductor device.

Chemical Mechanical Planarization

This section covers chemical mechanical planarization (CMP). We discuss the tools, methods, and materials used for CMP.

Lithography - Introduction

This section provides an overview of lithography. It describes basic concepts such as optics, resist, and printing.

Lithography - Resolution

This section discusses resolution as it applies to lithography. It covers properties of light, diffraction, phase shift masking, and optical proximity correction.

Lithography - Resists

This section covers both positive and negative resists for lithography. It also covers hard mask technology.

Lithography - Subwavelength Issues

This section provides a quick review of wavelength, numerical aperture, and k-factors, and their relationship to lithography. The material provides an overview of immersion lithography. This section also covers techniques currently used while waiting for the transition to Extreme Ultraviolet Lithography (EUVL) like source optimization, mask engineering techniques like subwavelength resolution assist features, and double patterning approaches. It concludes with an overview of EUVL, discussing its advantages and disadvantages.

Lithography - Future

This section covers the future of lithography. It includes discussions on EUVL, SCALPEL, X-ray lithography, nano-imprint lithography, and immersion lithography.

LOCOS and STI

This section provides an overview of the basic process integration steps associated with transistor isolation. Specifically, we discuss LOCal Oxidation of Silicon (LOCOS) and Shallow Trench Isolation (STI).

Salicide and BEOL

This section provides an overview of the salicide process and the contact formation process.

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Chip Fabrication Process

Micronas Wafer FAB

Packaging

Introduction

Semiconductor packaging provides 4 key features for the semiconductor component. They include:

  • Protection for the semiconductor chip against mechanical damage, the influence of light, and some protection against changes due to moisture and contamination
  • The ability to interface the chip electrical function to the next level assembly
  • A path to remove heat from the chip
  • A form factor that can be handled during the assembly process at the next integration level.

We cover the basic design process, information on the individual steps like wire bonding and die attach, and information on the materials, like mold compound and leadframes.

Please click on the topics to the left to begin learning about this fascinating process.

Presentations

Assembly and Packaging Process Introduction

Package Types

This section describes basic package types. Some of these package types have been in use for several decades. This includes leaded packages, ball grid array (BGA) packages, flip-chip packages, pin grid array (PGA) packages, leadless chip carrier (LCC) packages, and land grid arrays. This section covers both ceramic and plastic versions of these packages.

Package Design Principles

This section provides an introduction to the packaging design process. Package design involves knowledge from several disciplines, including electrical engineering, mechanical engineering, industrical engineering, and materials science. This section briefly explains the activities performed by the package design engineer and tools used by the package design engineer.

Leadframes

This section covers information on how one manufactures a leadframe for traditional leadframe products like Dual Inline Packages (DIPS), Quad Flat Packs (QFPs), and the like. We cover the leadframe materials, the two main processes of stamp and etch, the plating options, and the impact of surface roughness on bonding.

Wire Bonding

Lead Finish and Trim, Solder Ball Attach

Die Attach

This section covers information on die attach materials and dispense techniques. We primarily cover silver epoxies, and discuss their storage, use and issues associated with pattern dispense. We also discuss curing processes and issues associated with adhesion.

Transfer Molding

This section covers the molding process used for semiconductor packaging. We include information on the overall process, the equipment and materials used for transfer molding, and the materials properties. We also describe characterization techniques, and modeling and simulation approaches. Finally, we discuss future materials for molding processes.

Packaging Business Issues

This section provides an introduction to the packaging design process. Package design involves knowledge from several disciplines, including electrical engineering, mechanical engineering, industrical engineering, and materials science. This section briefly explains the activities performed by the package design engineer and tools used by the package design engineer.

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Testing

Introduction

This workspace covers semiconductor and integrated circuit test. Test is a critical aspect of the design and manufacturing process. Test allows one to determine if the device is working correctly, and it can also give insight into potential failure mechanisms and manufacturing issues. In this section we cover: defect modeling, design for test, digital testing, analog testing, parametric testing, and test hardware.

Please click on the topics to the left to begin learning about this fascinating process.

Presentations

Automatic Testing Overview

This section introduces the concept of automatic testing of integrated circuits. It provides an overview of why testing is performed, and the equipment used to test ICs.

Boundary Scan Overview

This section introduces the boundary scan standard (IEEE 1149.1). It explains the use of boundary scan and discusses the ports, the test access protocol and the basic state diagram for the controller.

Defect Classes

This section covers defect classes and the electrical behavior of these defect classes. We concentrate on the bridging defect class, the delay defect class, and the open defect classes.

Test Process Basics

Test process basics provides an overview of the test process and how defect-based test fits into it. This section covers the development of the test set from design through to production and the various components of test. It also discusses approaches such as random test pattern generation, and scan-based approaches for combinational and sequential circuits.

Stuck-At-Fault Testing

This section briefly describes the stuck-at fault model and how it works. It also provides a simple example and a discussion on how to create a computer algorithm based on the concept.

Timing Tests in Production

The most common, and most difficult, parametric defects to detect are timing problems. Timing problems require strategies such as varying the frequency of the IC under test, and changing the clocking signals in the scan circuitry. We discuss these techniques in more detail in this section.

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IDDQ Testing

4-Day Failure Analysis Course (Online Version)

  1. The seminar will provide participants with an in-depth understanding of the tools, techniques and processes used in failure and yield analysis.
  2. Participants will be able to determine how to proceed with a submitted request for analysis, ensuring the analysis is done with the greatest probability of success.
  3. The seminar will identify the advantages and disadvantages of a wide variety of tools and techniques that are used for failure and yield analysis.
  4. The seminar offers a wide variety of video demonstrations of analysis techniques, so the analyst can get an understanding of the types of results they might expect to see with their equipment.
  5. Participants will be able to identify basic technology features on semiconductor devices.
  6. Participants will be able to identify a variety of different failure mechanisms and how they manifest themselves.
  7. Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

Day 1 Courses

In day 1 we cover several important topics. We begin with an overview of failure analysis. We describe the reasons for performing failure analysis, and provide a brief history, contrasting the approaches for failure analysis 30 years ago with today's approaches. We then cover both philosophical and practical principles for failure analysis. We then describe notional analysis flows for basic, routine, and in-depth analysis work for both packaged parts and wafers. We then move on and describe the background information required to increase the chances for successful analysis work. Next, we cover package level analysis techniques. These include the major non-destructive analysis techniques like x-ray radiography, acoustic microscopy, time-domain reflectometry, and SQUID microscopy. We also briefly address destructive techniques like Particle Impact Noise Detection (PIND), leak testing, and Residual Gas Analysis (RGA). To wrap up day 1 we cover electrical testing techniques. This includes an overview of semiconductor device operation, a look at the electrical behavior of defects, the operation of the curve tracer, and a number of troubleshooting techniques for digital and analog circuits, microprocessors, and memories.

Presentations

Principles and Procedures - Part 1

This section covers some basic information regarding the evolution of failure analysis over the past 40 years. It also lists the basic philosophical and practical principles associated with failure analysis.

Principles and Procedures - Part 2

This section covers the top level flowcharts associated with both packaged part failure analysis and wafer or die level yield analysis.

Principles and Procedures - Part 3

This section covers the second level flowcharts associated with particular activities such as electrical characterization, package characterization, fault isolation at the chip level, defect localization at the gate/interconnect level, and materials characterization.

Quiz: Principles and Procedures

This quiz reviews the basic concepts associated with the philosophy, practical rules, and procedures of failure analysis.

Gathering Background Information

This section describes the process an analyst should use to collect the necessary and salient information to perform the failure analysis efficiently.

Gathering Background Information

This section describes the process an analyst should use to collect the necessary and salient information to perform the failure analysis efficiently.

Package Inspection Techniques - Overview

This section covers the basics of plastic and ceramic packaging technologies. It includes a discussion of wirebonding, die attach, and package lead-frame construction.

Package Inspection Techniques - Part 2

This section covers the use of optical imaging for examination of package-related failures.

Package Inspection Techniques - Part 3

This section covers x-ray radiography and micro-focus x-ray imaging. This technique can identify packaging flaws, contamination, and voids.

Package Inspection Techniques - Part 4

This section covers scanning acoustic microscopy. This technique can identify interface problems and delaminations.

Package Inspection Techniques - Part 5

This section covers techniques used to evaluate package cavities. The techniques discussed include: hermetic seal testing, particle impact noise detection, and residual gas analysis.

Package Analysis Techniques Quiz

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Basic Circuit Eletrical Behavior

This section covers basic device and transistor operation. It includes a discussion on the parasitic elements associated with the bipolar junction and MOS transistor.

Curve Tracer Part 1

This section describes how to use both the Tektronix 576 and Agilent 4145/4156 series instruments. We go into detail to describe the instrument panels and how they operate.

Eletrical Testing - IDDQ and Test Equipment

This section covers a test technique called quiescent power supply current (IDDQ). It also covers an introduction to automatic test equipment.

Quiz: Eletrical Testing

Digital Troubleshooting

This section covers techniques for troubleshooting basic digital logic. It includes methods for backtracing in combinational logic, locating problems in sequential logic, and identifying hazards in race conditions.

Analog Troubleshooting

This section covers techniques for troubleshooting analog circuits such as voltage references, operational amplifiers, digital to analog and analog to digital converters.

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Day 2 Courses

In day 2 we cover package access, die inspection and light emission. We begin with the package access techniques. This includes both front and backside access techniques. Frontside access techniques include chemical decapsulation, laser decapsulation, and a variety of mechanical decapsulation techniques. Backside access techniques include standard grinding and polishing, Computer Numerically-Controlled (CNC) milling, and reactive ion etching. We also briefly discuss FIB and Laser Microchemical techniques. The die inspection techniques include optical microscopy for quick, frontside viewing, infrared microscopy for quick backside viewing, and scanning electron microscopy for high-resolution, surface imaging. Light emission is the first of the fault isolation techniques we cover in this course. It is a passive technique that allows the analyst to view low levels of light or photons eminating from structures. These emission signatures can be related to the failure of the circuit, and we discuss how to interpret them. Finally, we discuss Time-resolved light emission, a technique for inferring the waveforms and the timing operation of the circuit.

Presentations

Backside Sample Preparation - Part 1

This section covers a number of techniques used for decapping integrated circuits and semiconductor devices. It includes mechanical, chemical, and thermal techniques.

Backside Sample Preparation - Part 2

This section covers the use of mechanical grinding and polilshing as a backside sample preparation technique. It also covers the use of computer numerically-controlled milling, and reactive ion etching.

Backside Sample Preparation - Part 3

This section covers the use of the focused ion beam and laser microchemical technique for preparing local areas from the backside.

Quiz: Package Decapsulation and Backside Sample Preparation

Optical Microscopy

This course covers the physics and applications of optical microscopy to semiconductor failure analysis. The topics include bright field imaging, dark field imaging, and interference contrast imaging.

Optical and SEM Inspection Quiz

Light Emission Microscopy - Part 1

This course provides a short introduction to light emission microscopy.

Light Emission Microscopy - Part 2

This course covers the physics of light emission, including: radiative and non-radiative recombination, and hot carrier effects. The course also covers the topic of spectral light emission.

Light Emission Microscopy - Part 3

This course covers the two major classes of camera systems used for light emission microscopy: intensified cameras and charged-coupled device (CCD) cameras.

Light Emission Microscopy - Part 4

This course covers the applications and issues surrounding light emission microscopy. The topics include: what types of gates and bias conditions result in light emission, where light emission is observed, and stimulus techniques.

Light Emission Microscopy - Part 5

This course covers time resolved light emission, including the original PICA technique and the more sensitive single point detection methods.

Light Emission Quiz

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Day 3 Courses

In day 3 we cover the rest of the fault localization techniques as well as deprocessing techniques. We begin with electron beam techniques, which include voltage contrast, Electron Beam Induced Current (EBIC), Resistive Contrast Imaging (RCI), and Charge Induced Voltage Alteration (CIVA). We then cover optical beam techniques like Optical Beam Induced Current (OBIC), Light Induced Voltage Alteration (LIVA), Seebeck Effect Imaging and Thermally Induced Voltage Alteration/Optical Beam Induced Resistance Change (TIVA/OBIRCH). We also cover Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP). We then move on to thermal detection techniques like Infrared Thermography, Liquid Crystal Hot Spot Detection, and Fluorescent Microthermal Imaging (FMI). We end this day by covering a variety of techniques for deprocessing chips, which include chemical etching, parallel polishing, reactive ion etching, cross-sectioning techniques, and tools for automated sample preparation.

Presentations

Voltage Contrast

This course covers the various types of voltage contrast used in the analysis of semiconductor devices, including: passive voltage contrast, static voltage contrast, capacitive-coupled voltage contrast, and electron beam probing.

Electron Beam Induced Current

This course covers the physics and applications of Electron Beam Induced Current (EBIC).

Resistive Contrast Imaging

This course covers the physics and applications of a technique related to Electron Beam Induced Current called Resistive Contrast Imaging (RCI).

Charge-Induced Voltage Alteration

This course covers the physics and applications of Charge Induced Voltage Alteration (CIVA).

Electron Beam Techniques Quiz

Optical Beam Techniques - Part 1

This course covers optical beam induced current (OBIC) and a more sensitive technique that uses constant current biasing called light induced voltage alteration, or LIVA. OBIC is useful for imaging junctions and defects associated with junctions. LIVA is useful for imaging junctions, and defects connected to junctions, including open circuits. Both OBIC and LIVA can be used from the front and back side of the semiconductor.

Optical Beam Techniques - Part 2

This course covers Seebeck effect imaging. Seebeck effecting imaging is useful for localizing open interconnect, both from the front side and back side of the semiconductor device.

Optical Beam Techniques - Part 3

This course covers thermally-induced voltage alteration (TIVA). TIVA is useful for localizing shorts and resistance changes from the front side or back side of the semiconductor device.

Optical Beam Techniques - Part 4

This course covers electro-optical probing techniques, including techniques that use the Kerr effect, the Pockels effect, and the Franz-Keldysh effect. It also covers the laser voltage probe (IDS-2K).

Optical Beam Techniques - Part 5

This course covers soft defect localization. Soft defect localization is a class of techniques that use laser stimulation and ATE pass-fail status to localize defects. Topics include resistive interconnect localization, identifying timing problems, and design/manufacturing interactions that impact functionality.

Optical Beam Techniques Quiz

Thermal Detection Techniques - Part 2

This section covers the basics of blackbody radiation and infrared thermography. Infrared thermography is a non-contact thermal detection technique.

Thermal Detection Techniques - Part 3

This section covers liquid crystal thermography. It is a real-time temperature technique that allows one to sense regions above the clearing point of a liquid crystal.

Thermal Detection Techniques Quiz

This quiz tests the student's knowledge of the three main thermal detection techniques: Liquid Crystal Hot Spot Detection, Infrared Thermography, and Fluorescent Microthermal Imaging.

Sample Preparation - Part 1

This course provides an introduction to the various types of deprocessing - chemical etching, parallel polishing, cross-sectioning, and plasma/reactive ion etching. It also provides reasons for using one approach over another.

Sample Preparation - Part 2

This course covers chemical etching techniques for silicon, silicon dioxide, silicon nitride, aluminum, copper and other metals.

Sample Preparation - Part 3

This course covers parallel polishing techniques for removing interconnect and dielectric layers from an IC to expose underlying interconnect and circuitry.

Sample Preparation - Part 4

This course covers grinding and polishing techniques for preparing cross section samples.

Sample Preparation - Part 5

This course covers plasma and reactive etching ion principles, as well as techniques, recipes and issues related to removing both dielectric and metal layers from circuits.

Sample Preparation - Part 6

This course covers automated techniques for SEM sample preparation, TEM sample preparation, and TEM lift-out.

Sample Preparation - Part 7

This course covers chemical safety, including personal protective equipment, engineered barriers like fume hoods, chemical storage, handling, and disposal.

Deprocessing Quiz

This quiz tests the student's knowledge of semiconductor deprocessing techniques.

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Fluorescent Microthermal Imaging

Day 4 Courses

In day 4 we primarily cover analytical characterization techniques. We begin by discussing the Scanning Probe Microscope (SPM). While there are a number of techniques that can be performed with this approach, these instruments have limited scan fields and slow scan rates. However, techniques like Atomic Force Microscopy (AFM), Scanning Capacitance Microscopy (SCM) and others are used routinely for semiconductor characterization and failure analysis. We then discuss other surface analytical techniques like Energy Dispersive Spectroscopy (EDS), Electron Energy Loss Spectroscopy (EELS), Fourier Transform Infrared Spectroscopy (FTIR), and Secondary Ion Mass Spectroscopy (SIMS). We also discuss the Transmission Electron Microscope (TEM), which is primarily used for cross-section imaging. We discuss the Focused Ion Beam System (FIB), and its uses in circuit editing, cross-sectioning, circuit repair, and imaging. Then we briefly discuss some of the more important failure mechanisms encountered in FA, and we end with several case studies, which bring all of the concepts together that we learned over the course.

Presentations

Scanned Probe Techniques - Part 1

This section introduces the topic of scanning probe microscopy. We cover the basic concept behind scanned probe techniques, and briefly describe many of the techniques that have been developed in this area. We describe tip interaction with the sample surface. We also introduce the two major techniques for mapping topography, scanning tunneling microscopy and atomic force microscopy.

Scanned Probe Techniques - Part 2

This section covers several important scanned probe techniques that are used in semiconductor characterization. We discuss scanning capacitance microscopy, magnetic force microscopy, electrostatic force measurement, and near field scanning optical microscopy.

SPM Techniques Quiz

Analytical Techniques - Basic

This section provides an overview of several materials analysis techniques that are used to characterize semiconductor devices and surface contamination. It includes brief discussions on Energy Dispersive Spectroscopy (EDS), Wavelength Dispersive Spectroscopy (WDS), and Electron Energy Loss Spectroscopy (EELS).

Analytical Techniques - Advanced

This section provides an overview of some additional materials analysis techniques that are used to characterize semiconductor devices and surface contamination. It includes brief discussions on Auger Electron Spectroscopy (AES), Electron Spectroscopy for Chemical Analysis/X-Ray Photoelectron Spectroscopy (ESCA/XPS), and Rutherford Backscattering Spectroscopy (RBS), Total X-Ray Fluorescence (TXRF), Glow Discharge Mass Spectroscopy (GDMS) and Secondary Ion Mass Spectroscopy (SIMS).

Analytical Techniques - Imaging

This section provides an overview of two imaging techniques used in materials characterization: Transmission Electron Microscopy (TEM) and Scanning Transmission Electron Microscopy (STEM). We discuss the basics behind the technique and some issues related to their operation and interpreting the images.

Analytical Techniques Quiz

Focused Ion Beam Technology - Part 1

In this section we introduce the Focused Ion Beam (FIB) system. We show the system from a high-level schematic point of view, and then discuss the Liquid Metal Ion Source, which provides the ions for milling and imaging.

FIB Techniques Quiz

Hot Carrier Degradation - Overview

This section talks about the historical failure mechanism known as hot carrier degradation. It describes how it occurs, and the techniques used to mitigate its effects. Today, hot carrier effects are largely contained by scaling the voltage on the IC.

Electromigration

This section discusses electromigration as it applies to aluminum interconnect and vias. We discuss the models and the effects of barrier layers, metal sandwich structures, and multiple contacts.

Stress Induced Voiding

This presentation covers the basic concept of stress induced voiding. We cover the physical mechanism and the main model used to understand this mechanism.

Eletrical Overstress and ESD

Overstress and ESD are common system-level problems that can affect semiconductor devices. There are four major overstress mechanisms: gross overstress, electrostatic discharge (ESD), latch-up, and snapback.

Moisture and Corrosion

Moisture represents a significant threat to semiconductor reliability. A number of materials used in the semiconductor manufacturing and packaging processes can react with moisture (or moisture and an electric potential) and corrode. This section discusses this reliability mechanism.

Thermomechanical Stress - Part 1

Thermomechanical stress is a group of failure mechanisms that are caused by the combination of mismatches in coefficients of thermal expansion between materials in the semiconductor component and thermal cycling or thermal excursions. These mechanisms include stresses to the bond wires, interactions between the die surface and the plastic encapsulating material, and stresses to the die itself.

Basic Failure Mechanisms

Failure Analysis Case Histories

This case history covers several integrated circuit failures that were observed at electrical test after packaging.

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Final Exam

Now that you have completed the course presentations and quizzes, you're ready to take the final exam. This exam covers the materials you have learned in this class, and the answers to the questions should be available in the materials.

Presentations

FA Final Test

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4-Day Reliability Course (Online Version)

  1. The seminar will provide participants with an in-depth understanding of the failure mechanisms, test structures, equipment and testing methods used to achieve today's high reliability components.
  2. The participant will be able to gather data and determine how best to plot the data and make inferences from that data.
  3. The seminar will identify the major failure mechanisms, explain how they are observed, how they are modeled and how they are eliminated. There will be a particular emphasis on electromogration and package level failure mechanisms.
  4. The seminar offers a variety of video demonstration of analysis techniques, so that the analyst can get an understanding of the types of results they might expect to see with their equipment.
  5. The participant will be able to identify basic test structures and how they are used to help quantify reliability on Semiconductor devices.
  6. The participant will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.
  7. The participant will be able to identify appropriate tools to purchase when starting or expanding a laboratory.
  8. In this course, we will concentrate in particular on electromigration. The customer has identified electromigration as a particular concern and area where they need additional knowledge.

Day 1 Courses

Day 1 covers an introduction to reliability as well as statistics and distributions. We begin with an overview of basic terms and definitions used in reliability and provide a brief history of the major themes throughout the 50 year history of semiconductor reliability. We then cover statistics and distributions. We discuss the fundamentals of a distribution and how they can be displayed. We discuss the four major distributions used in semiconductor reliability: the Exponential distribution, the Weibull distribution, the Normal distribution, and the Lognormal distribution. We discuss the relationship between the Probability Density Function (PDF) the Cumulative Distribution Function (CDF) and Reliability. We also cover topics like acceleration and how it can affect a reliability calculation, and the mathematics behind interpreting a discrete number of failures and its implication on a large population.

Presentations

Introduction to Semiconductor Reliability

This section provides a history of reliability activities, introduces basic terminology, and discusses the link between reliability and yield.

Acceleration and Number of Failures

Plotting Data

Reliability Distribution Types

Basic Reliability Statistics

Reliability Statistics - Acceleration

This section covers acceleration and the process for determining estimated lifetimes from accelerated test data.

Reliability Statistics - Sample Size

This section covers concept of sample size and how to determine the number of failures and number of samples to stress to achieve a particular reliability level.

Which Distribution Should I Use?

This section covers the issues associated with choosing a distribution to fit a given set of data.

Documents

Reliability Distributions

This Excel workbook contains the basic graphs for the normal, lognormal, exponential, and Weibull distributions.

Reliability Distribution Examples

This Excel workbook contains an example set of data graphed using the normal, lognormal, exponential, and Weibull distributions.

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Day 2 Courses

Day 2 covers the die-level failure mechanisms. We concentrate on the major areas which include dielectric breakdown, transistor effects like hot carrier degradation and Negative Bias Temperature Instability (NBTI), interconnect related problems such as Electromigration (EM) and Stress Induced Voiding (SIV), and mobile ionic contamination. For each of these failure mechanisms we provide an overview of the failure mechanism, its effect at the circuit level, the major model or models used to calculate the reliability associated with the mechanism, and the various effects of voltage, temperature, electric field, current density, frequency and duty cycle. We also discuss the effects of technology, materials, and scaling on these mechanisms.

Presentations

Time Dependant Dielectric Breakdown Overview

Time-Dependent Dielectric Breakdown, or TDDB as it is also known, is a mechanism that degrades thin oxides subjected to high electric fields. A high electric field stresses an oxide, producing damage in the form of traps. These traps can eventually cause increased leakage. Sufficient leakage can result in dielectric breakdown.

Hot Carrier Degradation - Overview

This section talks about the historical failure mechanism known as hot carrier degradation. It describes how it occurs, and the techniques used to mitigate its effects. Today, hot carrier effects are largely contained by scaling the voltage on the IC.

Electromigration

This section discusses electromigration as it applies to aluminum interconnect and vias. We discuss the models and the effects of barrier layers, metal sandwich structures, and multiple contacts.

Stress Induced Voiding - Case History

This presentation covers an example of stress voiding, how it was discovered and identified, and how it was eliminated from the process.

Stress Induced Voiding

This presentation covers the basic concept of stress induced voiding. We cover the physical mechanism and the main model used to understand this mechanism.

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Day 3 Courses

Day 3 covers the package-level and use condition failure mechanisms. The major groupings for the package-level failure mechanisms are moisture/corrosion, thermomechanical stress, and thermal degradation. We cover moisture/corrosion problems on the external leads, the leadframe internal to the package, and moisture problems that affect the die. We also cover the main model for moisture, known as the Peck Model, and formulas for estimating relative humidity, and cycling response. We cover thermomechanical mechanisms that include the popcorn effect, die cracking, package cracking, and the resulting problems like die and bondwire damage. We primarily cover intermetallic growth under thermal degradation. The use condition failure mechanisms we cover include Electrical Overstress (EOS), Electrostatic Discharge (ESD), Latch-Up (LU), snapback, and soft errors. Under soft errors, we primarily focus on Single Event Upset (SEU) issues.

Presentations

Ionic Contamination

This section talks about the historical failure mechanism known as ionic contamination. It is largely contained today by aggressively controlling cleanliness in the fab, removing human handling, and using ultra-pure chemicals. This section covers the major technological approaches for reducing ionic contamination is the circuit as well.

Moisture and Corrosion

Moisture represents a significant threat to semiconductor reliability. A number of materials used in the semiconductor manufacturing and packaging processes can react with moisture (or moisture and an electric potential) and corrode. This section discusses this reliability mechanism.

Thermomechanical Stress - Part 1

Thermomechanical stress is a group of failure mechanisms that are caused by the combination of mismatches in coefficients of thermal expansion between materials in the semiconductor component and thermal cycling or thermal excursions. These mechanisms include stresses to the bond wires, interactions between the die surface and the plastic encapsulating material, and stresses to the die itself.

Thermomechanical Stress - Part 2

Thermomechanical stress is a group of failure mechanisms that are caused by the combination of mismatches in coefficients of thermal expansion between materials in the semiconductor component and thermal cycling or thermal excursions. These mechanisms include stresses to the bond wires, interactions between the die surface and the plastic encapsulating material, and stresses to the die itself.

Thermal Degradation

Thermal degradation is a class of failure mechanisms that result in materials problems. At elevated temperatures some alloys can form that can have detrimental effects on the physical and/or electrical properties of a semiconductor component. Examples of this type of failure mechanism include intermetallic formation, or purple plague, and lead finish degradation.

Electrical Overstress and ESD

Overstress and ESD are common system-level problems that can affect semiconductor devices. There are four major overstress mechanisms: gross overstress, electrostatic discharge (ESD), latch-up, and snapback.

Radiation Effects

Radiation effects are a growing concern in many microelectronic devices. The most common radiation effect is the Single Event Upset or SEU. This can cause temporary errors in memories and logic path corruption in microprocessors. Another effect is charge build-up in oxides that can result in performance degradation.

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Day 4 Courses

Day 4 covers testing aspects of semiconductor reliability. We begin by covering test structures. We discuss the main purpose for test structures, and then show various test structures that can be used for Wafer Level Reliability (WLR) testing. We then cover the equipment used for reliability testing. We discuss probers, probe stations, source-measurement units and integrated reliability test systems for WLR testing. We then discuss the probe cards and probes used for WLR testing. We also discuss the probe needles themselves. The final portion of the reliability equipment section covers packaged-part test systems for both burn-in as Highly Accelerated Stress Testing (HAST). We then cover the reliability tests. This includes a general look at burn-in, life testing, and stress testing. We briefly cover the JEDEC tests associated with product qualification as well.

Presentations

Test Structures - Basics

This section covers basic test structures and their use for reliability characterization. It also includes basic information on the purpose of test structures.

Reliability Test Structures

This section covers test structures that are designed specifically for reliability characterization. This section describes TDDB-specific structures and how they can be designed to help separate and identify different effects.

Self Stressing Test Structures

This section covers self-stressing test structures and their use in more accurately characterizing reliability degradation mechanisms.

Reliability Test Equipment - Wafer Level

This section covers wafer level reliability test equipment. It includes material on probers, source measurement units, switch matrices, and software.

Reliability Test Equipment - Probes

This section covers probe card and probe tip technology for wafer level probing.

Reliability Test Equipment - Packaged Parts

This section covers reliability test equipment that is designed for testing packaged ICs. It includes discussions on burn-in equipment, humidity testing, and other reliability-related testing.

Developing Electrical Screens

This section covers electrical and parametric screens that are performed to aid in the reliability evaluation of an IC.

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Final Exam

Now that you have completed the course presentations and quizzes, you're ready to take the final exam. This exam covers the materials you have learned in this class, and the answers to the questions should be available in the materials.

Presentations

Semiconductor Reliability - Final Exam

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Analysis - Die Level

Die Level Failure Analysis

In the past, many problems on semiconductor components could be located and diagnosed using an optical microscope, or a scanning electron microscope. Today’s complex integrated circuits can be much more difficult to analyze. This requires a number of defect localization techniques. These techniques include: electron beam techniques, optical beam techniques, photon emission microscopy or light emission, scanned probe techniques, and thermal detection techniques. In addition, one must be able to expose and connect to the area of interest. Chemical unlayering techniques continue to be important; however, a newer tool is rapidly gaining use in this arena - the focused ion beam system.

Chemical Unlayering

Deprocessing and Sample Preparation are important parts of the failure analysis process. Deprocessing is used to expose underlying layers for examination and characterization and viewing cross-sectioned surfaces. These courses provide information on how to deprocess circuits using chemical etches, plasma and reactive ion etches, and parallel polishing techniques. There is also a course discussing how to cross section circuits. Another course provides information on automated cross-sectioning techniques and TEM sample preparation. A final course provides information on chemical safety.

Presentations

Sample Preparation - Part 1

This course provides an introduction to the various types of deprocessing - chemical etching, parallel polishing, cross-sectioning, and plasma/reactive ion etching. It also provides reasons for using one approach over another.

Sample Preparation - Part 2

This course covers chemical etching techniques for silicon, silicon dioxide, silicon nitride, aluminum, copper and other metals.

Sample Preparation - Part 3

This course covers parallel polishing techniques for removing interconnect and dielectric layers from an IC to expose underlying interconnect and circuitry.

Sample Preparation - Part 4

This course covers grinding and polishing techniques for preparing cross section samples.

Sample Preparation - Part 5

This course covers plasma and reactive etching ion principles, as well as techniques, recipes and issues related to removing both dielectric and metal layers from circuits.

Sample Preparation - Part 6

This course covers automated techniques for SEM sample preparation, TEM sample preparation, and TEM lift-out.

Sample Preparation - Part 7

This course covers chemical safety, including personal protective equipment, engineered barriers like fume hoods, chemical storage, handling, and disposal.

Deprocessing Quiz

This quiz tests the student's knowledge of semiconductor deprocessing techniques.

Documents

Chemical Unlayering

This material contains a discussion of chemical and mechanical deprocessing, including wet chemical etching, reactive ion etching, and parallel polishing. Topics include: chemical deprocessing, mechanical deprocessing, chemical etching, silicon etch chemistry, dieletric removal, decoration etches, decoration stains, metal interconnect, polysilicon etches, gallium arsenide etch chemistry, reactive ion etches, silicon dioxide etches, parallel lapping, die backside polishing.

Trion Phantom Ion Etch System Simulation

This simulation demonstrates how the Trion Phantom Reactive Ion Etch System works and how the variables affect the etching time and process.

Videos

Passivation Removal - Reactive Ion Etch Method

This short video clip demonstrates how to use a reactive ion etch system to remove the top dielectric layer from an integrated circuit.

Acid Decapsulation

Reactive Ion Etch - Overview

Electron Beam Techniques

Electron Beam Techniques are a class of fault localization techniques that utilize a scanning electron microscope. These techniques rely on the interaction of the electron beam with the sample while monitoring an aspect of the electrical behavior of the circuit. These techniques include: charge-induced voltage alteration or CIVA, electron beam induced current or EBIC, resistive contrast imaging or RCI, and several variants of voltage contrast.

Presentations

Voltage Contrast

This course covers the various types of voltage contrast used in the analysis of semiconductor devices, including: passive voltage contrast, static voltage contrast, capacitive-coupled voltage contrast, and electron beam probing.

Electron Beam Induced Current

This course covers the physics and applications of Electron Beam Induced Current (EBIC).

Resistive Contrast Imaging

This course covers the physics and applications of a technique related to Electron Beam Induced Current called Resistive Contrast Imaging (RCI).

Charge-Induced Voltage Alteration

This course covers the physics and applications of Charge Induced Voltage Alteration (CIVA).

Low Energy Charge Induced Voltage Alteration

This course covers the physics and applications of a technique related to Charge Induced Voltage Alteration called Low Energy Charge Induced Voltage Alteration (LECIVA).

Electron Beam Absorbed Current

Electron Beam Absorbed Current (EBAC) is a scanning electron microscope technique for identifying opens. This technique also went by the name Resistive Contrast Imaging (RCI) for a number of years. We discuss the physics behind the technique and show several examples of how it can be used to localize resistive and complete opens on integrated circuits, both with and without nanoprobing capabilities.

Electron Beam Techniques Quiz

Documents

Electron Beam Techniques

This material discusses various electron beam analysis tools, including: voltage contrast, secondary electron imaging, static voltage contrast, capacitive coupling voltage contrast, passive voltage contrast, electron beam probing, electron beam induced current, resistive contrast imaging, charge induced voltage alteration or CIVA.

Videos

Capacitive Coupled Voltage Contrast & Static Voltage Contrast

This video clip describes two electron beam techniques: capactive coupled voltage contrast, and static voltage contrast. Static voltage contrast allows one to observe differences in voltage levels on a depassivated IC, while capacitive coupled voltage contrast allows one to observe changing voltage conditions on a passivated IC.

CIVA

This video describes Charge-Induced Voltage Alteration and a variant called Low-Energy Charge-Induced Voltage Alteration. This technique is used to localize open conductors on integrated circuits.

Electron Beam Probing - Setup

This video describes the basic setup required for electron beam probing. We discuss how to mount the IC in the system, how to establish a vector loop for imaging and waveform acquisition, and the need for proper cabling between the tester and the electron beam prober.

Electron Beam Probing - Imaging

This video describes how to obtain a good image for observing voltage contrast. We discuss focusing, lens alignment, gun alignment, and other factors that help improve imaging.

Electron Beam Probing - Waveform Acquisition

This video describes how to obtain a waveform from an operating circuit. We discuss how to place the probe for best waveform quality, and how factors like cross talk and depth of the signal play a role in the quality of the waveform.

Resistive Contrast Imaging

This video describes the Resistive Image Contrast (RCI) technique and shows how to acquire an RCI image.

Nanoprobing

FIB

Introduction

The focused ion beam (FIB) system has become an indispensable tool for failure analysis, design debug, and circuit editing. The FIB allows one to make modifications to a circuit and test them before generating new masks for a chip design. This can save millions of dollars in mask and wafer processing costs. The FIB is also used for TEM sample preparation, cross-sectioning, and other types of micromachining activities.

Presentations

Focused Ion Beam Technology - Part 1

In this section we introduce the Focused Ion Beam (FIB) system. We show the system from a high-level schematic point of view, and then discuss the Liquid Metal Ion Source, which provides the ions for milling and imaging.

Focused Ion Beam Technology - Part 2

In this section we discuss the applications of Focused Ion Beam Technology. We discuss how one performs milling to cut a line, milling to create a cross section, milling to create a lamella for TEM imaging, deposition for creating connections, and the process of doing circuit edits, both from the front side and the back side.

FIB Techniques Quiz

Documents

FIB Technology

This material covers focused ion beam technology. The material covers the physics, instrumentation, and applications of the focused ion beam (FIB) system. Topics include: physics of operation and imaging, FIB of applications and considerations, electrical circuit irradiation effects and countermeasures, future FIB developments.

Videos

FIB System Overview

This video gives an overview of the Focused Ion Beam (FIB) system. We describe the various components of the FIB system, and show how one can perform a basic operation like milling or deposition.

Circuit Editing & Cross Sectioning

This video demonstrates how to perform a cross section with the Focused Ion Beam (FIB) system. We describe the basic steps in the process, and how to obtain the best image of the cross-sectioned surface. The video also demonstrates how to perform a basic circuit edit. We discuss the procedure for milling depositions to make connections, and milling to break connections. We also discuss why we make connections before breaking connections.

Inspection

Introduction

Die inspection is arguably one of the most important aspects of any failure analysis job. Die inspection is normally where one first generates an image of the defect, whether it be immediately after opening the sample or preparing the die for backside inspection, or after one or more layers have been removed. Die inspection is performed using three techniques: optical microscopy, infrared microscopy, and scanning electron microscopy. Optical microscopy is performed on the front side of semiconductor devices; infrared microscopy is performed from the backside, and scanning electron microscopy is performed on surface features.

Presentations

Infrared Microscopy

This course covers the applications of infrared microscopy for failure analysis. Infrared microscopy allows examination of silicon devices from the backside.

Optical Microscopy

This course covers the physics and applications of optical microscopy to semiconductor failure analysis. The topics include bright field imaging, dark field imaging, and interference contrast imaging.

Scanning Electron Microscopy

This course covers scanning electron microscopy for imaging purposes. Topics include the physics of SEM imaging, secondary electron imaging, backscattered electron imaging, and applications.

Optical and SEM Inspection Quiz

Solid Immersion Lenses

Documents

Inspection

This material provides an overview of Optical and SEM Inspection, including topics such as bright field microscopy, dark field microscopy, Nomarski or interference contrast microscopy, infrared microscopy, scanning electron microscopy, electron beam sample interaction physics, secondary electron imaging, and backscattered electron imaging.

Videos

Optical Microscopy - Brightfield, Darkfield, and Interference Contrast Imaging; How To Take A Picture; Determining Oxide Cuts

Part 1 of this video shows how to perform basic brightfield imaging, darkfield imaging and interference contrast imaging. We show a test structure and how the different imaging modes affect the result. Part 2 of this video shows how to take a Polaroid image with older microscope systems. Part 3 of this video shows how to identify an opening in the top passivation (dielectric) on a bond pad. This can be useful for determining if an etch has removed the top dielectric layer.

UV Fluorescene

This video shows how one can identify polymers using ultraviolet (UV) light. UV light will cause some polymers to fluoresce, making them easier to identify in an optical image. This does require a specialized microscope with UV objectives and a UV source.

Nomarski Imaging of Bond Pads

This video shows how to use Nomarski imaging (also known as Interference Contrast Imaging) to identify subsurface defects in large structures, such as bond pads.

Low Power Optical Microscopy

This video shows how one can use low power optical microscopy to examine components. We discuss image capture as well as lighting conditions. Lighting is particularly important and sometime challenging with packaged devices.

Scanning Electron Microscopy Overview

This video describes the basic operation of the Scanning Electron Microscope (SEM). We discuss the instrument, loading and unloading samples, and imaging. In particular we discuss some of the factors that go into creating a high quality image, like focus, astigmatism, lens alignment, gun alignment, accelerating voltage, current, and so on.

Light Emission

Introduction

Light Emission Microscopy is a powerful technique for fault localization at the die level. Light Emission Microscopy uses an image intensifier or a cooled semiconductor array camera to detect light emanating from a semiconductor device. Many defects either emit light or cause emission in associated transistors. A variant of light emission called PICA can be used for inferring waveform information on an integrated circuit. Although the technique is quite powerful, interpretation of light emission data can be challenging. The analyst must possess a sound understanding of electrical circuit behavior as well as device recognition skills.

Presentations

Light Emission Microscopy - Part 1

This course provides a short introduction to light emission microscopy.

Light Emission Microscopy - Part 2

This course covers the physics of light emission, including: radiative and non-radiative recombination, and hot carrier effects. The course also covers the topic of spectral light emission.

Light Emission Microscopy - Part 3

This course covers the two major classes of camera systems used for light emission microscopy: intensified cameras and charged-coupled device (CCD) cameras.

Light Emission Microscopy - Part 4

This course covers the applications and issues surrounding light emission microscopy. The topics include: what types of gates and bias conditions result in light emission, where light emission is observed, and stimulus techniques.

Light Emission Microscopy - Part 5

This course covers time resolved light emission, including the original PICA technique and the more sensitive single point detection methods.

Light Emission Quiz

Documents

Light Emission Microscopy

This material discusses Photon Emission Microscopy (also known as Light Emission Microscopy). The topics include photon emission microscopy, theory of light emission from silicon ICs, PEM detectors, spectral analysis of light emission data, spectrometer theory of operation, forward biased pn junctions, reverse biased pn junctions, MOSFETs in saturation, latchup, gate oxide failures, effects of thin dielectric films on transmitted spectra, gate oxide failure example, polysilicon stringer example.

Videos

LEM

This video describes the two classical types of light emission systems: systems with image intensifiers, or night vision cameras, and systems with silicon charge-coupled device cameras. We show basic acquistion of images with both systems.

PICA Microprocessor & Ring Oscillator

This video shows some early examples of Picosecond Integrated Circuit Analysis (PICA) from IBM. This technique is also known as Time Resolved Emission. We show video loops of emission from a ring oscillator as well as a microprocessor.

Spectral Light Emission - Part 1

Setup

Spectral Light Emission - Part 2

Forward and reverse-biased diodes.

Spectral Light Emission - Part 3

ASIC burn-in failure.

Light Emission

Light Emission Process

Optical Beam Techniques

Introduction

Failure analysts now perform much of the fault localization work from the backside of the device. The complexity of the integrated circuits and the packaging has caused this transition. In order to penetrate the silicon, optical beam techniques are used. They are a class of techniques that rely on the interaction of an optical beam with the active devices or interconnect on the circuit. These include: electro-optical probing, light induced voltage alteration or LIVA, thermally induced voltage alteration or TIVA, optical beam induced current or OBIC, resistive interconnect localization and soft defect localization. The distinguishing feature of these techniques is that they require a scanning optical microscope system, and occasionally, complex stimulus, in the form of a properly chosen or designed vector set.

Presentations

Optical Beam Techniques - Part 1

This course covers optical beam induced current (OBIC) and a more sensitive technique that uses constant current biasing called light induced voltage alteration, or LIVA. OBIC is useful for imaging junctions and defects associated with junctions. LIVA is useful for imaging junctions, and defects connected to junctions, including open circuits. Both OBIC and LIVA can be used from the front and back side of the semiconductor.

Optical Beam Techniques - Part 2

This course covers Seebeck effect imaging. Seebeck effecting imaging is useful for localizing open interconnect, both from the front side and back side of the semiconductor device.

Optical Beam Techniques - Part 3

This course covers thermally-induced voltage alteration (TIVA). TIVA is useful for localizing shorts and resistance changes from the front side or back side of the semiconductor device.

Optical Beam Techniques - Part 4

This course covers electro-optical probing techniques, including techniques that use the Kerr effect, the Pockels effect, and the Franz-Keldysh effect. It also covers the laser voltage probe (IDS-2K).

Optical Beam Techniques - Part 5

This course covers soft defect localization. Soft defect localization is a class of techniques that use laser stimulation and ATE pass-fail status to localize defects. Topics include resistive interconnect localization, identifying timing problems, and design/manufacturing interactions that impact functionality.

Optical Beam Techniques Quiz

Solid Immersion Lenses

Documents

Optical Beam Techniques

Chapter discussing various optical beam tools. Examples of subjects covered are optical beam induced current, light-induced voltage alteration, seebeck effect imaging, thermally-induced voltage alteration, electro-optical probing, laser voltage probe.

Videos

LIVA 1 - Light Induced Voltage Operation

This video describes Light Induced Voltage Alteration (LIVA) and its use as a fault localization technique. We show the instrumentation and discuss how the image is formed, both from the front side as well as the back side.

LIVA 2 - Backside Logic State Detection

In this video we show the use of Light Induced Voltage Alteration (LIVA) to identify logic states on an SRAM array from the backside of the silicon.

LIVA 3 - Backside Examination Example

In this video we show the use of Light Induced Voltage Alteration (LIVA) to identify a short in an input/output (I/O) circuit from the backside of the silicon.

Seeback Effect Imaging

In this video we show the use of Seebeck Effect Imaging to localize an open in an interconnect segment from the backside of the IC. We also discuss the technique setup and instrumentation.

TIVA - Backside SRAM short

In this video we show the use of Thermally Induced Voltage Alteration (TIVA) to identify a short in a Static Random Access Memory (SRAM) from the backside of the silicon.

TIVA - Metal-2 Metal-3 Short

In this video we show the use of Thermally Induced Voltage Alteration (TIVA) to identify a Metal-2 to Metal-3 short in a Static Random Access Memory (SRAM) from the frontside of the silicon.

Scanned Probe Techniques

Introduction

The invention of the scanning tunneling microscope in 1981 has spawned a variety of instruments and techniques that fall under a category called Scanned Probe Techniques. Scanned Probe techniques involve micromachined tips that can be scanned with great precision over the surface of a device. These techniques can be used to look at the topography of a surface, and a variety of other phenomena such as electrical, magnetic, capacitive, thermal, and optical interactions.

Presentations

Scanned Probe Techniques - Part 1

This section introduces the topic of scanning probe microscopy. We cover the basic concept behind scanned probe techniques, and briefly describe many of the techniques that have been developed in this area. We describe tip interaction with the sample surface. We also introduce the two major techniques for mapping topography, scanning tunneling microscopy and atomic force microscopy.

Scanned Probe Techniques - Part 2

This section covers several important scanned probe techniques that are used in semiconductor characterization. We discuss scanning capacitance microscopy, magnetic force microscopy, electrostatic force measurement, and near field scanning optical microscopy.

SPM Techniques Quiz

Documents

Scanned Probe Techniques

Chapter covering different scanned probe techniques, including scanning probe microscopy, scanning tunneling microscopy, atomic force microscopy, scanning capacitance probe microscope, magnetic current microscopy, lateral force microscopy, scanning near field optical microscopy, superconducting quantum interference, device microscopy.

Videos

Atomic Force Microscope Setup

This video shows how to set up an Atomic Force Microscope (AFM) for imaging the surface of a sample. We discuss the various controls on this Veeco system for controlling scan rate, image quality, and the imaging mode.

Atomic Force Microscope Imaging

This video shows the results of imaging the surface of an IC using an Atomic Force Microscope. We show the normal imaging mode, as well as Electrostatic Force imaging.

Thermal Detection Techniques

Introduction

Thermal Detection Techniques are a class of techniques used to detect heat-generating defects on semiconductor devices. They are also occasionally used to verify thermal models of semiconductor components. The most popular of the thermal detection techniques are Infrared Thermography, Liquid Crystal Thermography, and Fluorescent Microthermal Imaging. Infrared Thermography is a sensitive, non-contact technique, but it lacks the spatial resolution needed for fine localization on semiconductor dice. Liquid Crystal Thermography has better spatial resolution, but only delineates temperatures above or below a certain temperature. Fluorescent Microthermal Imaging has good spatial resolution and thermal mapping capabilities, but is somewhat more difficult to use.

Presentations

Thermal Detection Techniques - Part 1

This section provides an overview of thermal detection techniques. It briefly discusses some of the less known thermal techniques such as the Schlieren technique, photodeflection thermal spectroscopy, thermoreflectance laser probing, internal infrared laser deflection, and the scanning thermocouple probe.

Thermal Detection Techniques - Part 2

This section covers the basics of blackbody radiation and infrared thermography. Infrared thermography is a non-contact thermal detection technique.

Thermal Detection Techniques - Part 3

This section covers liquid crystal thermography. It is a real-time temperature technique that allows one to sense regions above the clearing point of a liquid crystal.

Thermal Detection Techniques - Part 4

This section covers fluorescent microthermal imaging (FMI). FMI uses a temperature-sensitive compound to convert thermal data into visible light. It can be used to generate a temperature map of a semiconductor device.

Thermal Detection Techniques - Part 5

This section covers several examples using FMI to locate defects and regions of high current and power dissipation.

Liquid Crystal Thermography

This section shows how to set up and perform Liquid Crystal (LC) Thermography. We discuss the types of Liquid Crystal used for thermography, how to prepare the LC for use on a specimen, and how to interpret the data from the technique.

Thermal Detection Techniques Quiz

This quiz tests the student's knowledge of the three main thermal detection techniques: Liquid Crystal Hot Spot Detection, Infrared Thermography, and Fluorescent Microthermal Imaging.

Documents

Thermal Detection Techniques

Overview of several thermal detection techniques. Topics include blackbody radiation, infrared thermography, liquid crystal, flourescent microthermal imaging, EuTTA compound specifics, image processing, system hardware, photon shot noise, signal averaging, ultraviolet film bleaching, and scanning FMI.

Videos

Fluorescent Microthermal Imaging

This section shows how to set up and perform Fluorescent Microthermal Imaging on a sample. We show how the fluorescence works, how to identify the data, and how the instrumentation works for the technique. We use an electromigration test structure as an example to show how the sensitivity compares to Liquid Crystal Thermography.

Liquid Crystal Thermography

This video shows how to set up and perform Liquid Crystal Thermography on a sample. We use an electromigration test structure as an example to show how pulsing the signal through the structure can help localize the problem.

Analysis - Electrical

Electrical Analysis

Electrical analysis is critical to the success of most failure analysis work. In order to diagnose a problem with an integrated circuit one must be able to first reproduce the electrical failure mode, and second develop a simplified electrical test that will enable analysis using various techniques. This workspace covers basic device operation, curve tracer use, automatic test equipment, and electrical characteristics associated with trapped charge and mobile ionic contamination. It also covers techniques for troubleshooting a variety of microelectronic circuits including digital logic, memories, microprocessors and microcontrollers, and analog circuits. Finally, this section covers tools that can be used to automate the process of troubleshooting.

Curve Tracer

This section describes the use of a Curve Tracer/Semiconductor Parameter Analyzer for Failure Analysis. The material covers the examination of I/O structures and how to operate these instruments.

Presentations

Curve Tracer Part 1

This section describes how to use both the Tektronix 576 and Agilent 4145/4156 series instruments. We go into detail to describe the instrument panels and how they operate.

Curve Tracer Part 2

This section describes how to perform curve tracing on resistors, an ideal power supply, an ideal current source, as well as non-ideal supplies and sources. We also discuss additive and opposing sources, and sources in parallel. We also provide an example with sources in superposition.

Curve Tracer Part 3

This section covers how to perform curve tracing on diodes. We cover the forward bias and reverse bias conditions. We also give examples of diodes in series and in parallel with power supplies, current sources, and resistors.

Curve Tracer Part 4

This section covers how to perform curve tracing on transistors. We cover how to produce a family of curves using the base step generator. We also give examples of transistor biasing and how to interpret the curves.

Curve Tracer Quiz

This 15-question quiz provides a review of curve tracer operation and basic analysis of circuits containing voltage supplies, current supplies, resistors, diodes, and transistors.

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Videos

Curve Tracer - Examining a High Pin Count Device

This video shows how an automated curve tracer can be useful for gathering current-voltage (I-V) waveforms on a high pin count device. We show the fixturing for this type of work, how to set up the tests, and how to examine the resulting I-V waveforms.

Troubleshooting

This course contains material related to troubleshooting integrated circuits. Troubleshooting is an important part of the failure analysis process, and it is also critical for design debug activities. It covers digital integrated circuit troubleshooting techniques, analog integrated circuit troubleshooting techniques, basic microprocessor troubleshooting techniques, and memory troubleshooting techniques.

Presentations

DAC-ADC Troubleshooting

This section describes basic data converter troubleshooting techniques. It introduces both digital-to-analog and analog-to-digital converter topologies, and discusses where potential problems might lie with these devices.

Analog Troubleshooting

This section covers techniques for troubleshooting analog circuits such as voltage references, operational amplifiers, digital to analog and analog to digital converters.

Digital Troubleshooting

This section covers techniques for troubleshooting basic digital logic. It includes methods for backtracing in combinational logic, locating problems in sequential logic, and identifying hazards in race conditions.

Memory Troubleshooting

This section covers the test patterns and techniques used to troubleshoot static random access memory, dynamic random access memory, and non-volatile memory.

Microprocessor Troubleshooting

This section covers a technique used to troubleshoot both microprocessors and microcontrollers. It utilizes a concept called the fault window concept.

Quiz: Troubleshooting

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Videos

Microprobing with an Evaluation Board

Electrical Testing

Electrical testing is an integral part of product analysis activities. Most failures or problems manifest themselves as an incorrect electrical condition. This means that the analyst must be able to properly exercise the component to activate the defective condition. Once the defect can be activated, it can be further characterized to help determine the nature of the defect. An electrical condition can give clues as to the cause of the problem. Some troubleshooting techniques work intimately with electrical testing. These include defect localization techniques such as light emission and voltage contrast. Some of the electrical testing concepts that an analyst should be familiar with include: basics of circuit operation, curve tracer/semiconductor parameter analyzer operation, digital troubleshooting, analog troubleshooting, quiescent power supply current, and test equipment. Many of these topics are also covered in the test portion of our website.

Presentations

Basic Circuit Electrical Behavior

This section covers basic device and transistor operation. It includes a discussion on the parasitic elements associated with the bipolar junction and MOS transistor.

Electrical Testing - Electrical Properties of Defects

This section covers the electrical behavior of defects. It includes discussions on bridging defects, open circuit defects, and delay defects.

Electrical Testing - IDDQ and Test Equipment

This section covers a test technique called quiescent power supply current (IDDQ). It also covers an introduction to automatic test equipment.

Electrical Testing - Bakes

This section covers the methods and techniques for identifying moisture, mobile ionic contamination, and trapped charge using biased and unbiased bakes.

Quiz: Electrical Testing

Software Aids

This section covers software tools and techniques that can aid in the troubleshooting process. It includes discussions on automatic test pattern generation and fault dictionaries.

Documents

Electrical Testing

This chapter discusses various topics concerning electrical testing. Topics include: basics of circuit operation, discrete devices, transistors, integrated circuits, curve tracer and parameter analyzer operation, quiescent power supply current, parametric tests, timing tests, automatic test equipment, digital circuit troubleshooting, and analog circuit troubleshooting.

Videos

IDDQ Testing

Microprobing with an Evaluation Board

Nanoprobing

Analysis - Materials Characterization

Materials Characterization

Materials characterization is an important discipline within the semiconductor manufacturing field. One must be able to identify and characterize topography, vertical structures, aspect ratios, concentrations, dopant distributions, as well as defective conditions and foreign material. Materials characterization can loosely be divided into two groups: imaging techniques and materials analysis techniques.

Materials Characterization is occasionally used in failure analysis, and extensively used in yield analysis activities. There are a wide variety of techniques that allow examination of the device surface, as well as the top few microns of a sample. These include techniques like Auger Electron Spectroscopy, which is used for surface analysis, energy dispersive x-ray spectroscopy, which is used for analysis of the top 1 to 5 microns of a sample, Secondary Ion Mass Spectroscopy can be used for both surface analysis and depth profiling, and Transmission Electron Microscopy is used for high resolution imaging of prepared samples.

Presentations

Analytical Techniques - Basic

This section provides an overview of several materials analysis techniques that are used to characterize semiconductor devices and surface contamination. It includes brief discussions on Energy Dispersive Spectroscopy (EDS), Wavelength Dispersive Spectroscopy (WDS), and Electron Energy Loss Spectroscopy (EELS).

Analytical Techniques - Advanced

This section provides an overview of some additional materials analysis techniques that are used to characterize semiconductor devices and surface contamination. It includes brief discussions on Auger Electron Spectroscopy (AES), Electron Spectroscopy for Chemical Analysis/X-Ray Photoelectron Spectroscopy (ESCA/XPS), and Rutherford Backscattering Spectroscopy (RBS), Total X-Ray Fluorescence (TXRF), Glow Discharge Mass Spectroscopy (GDMS) and Secondary Ion Mass Spectroscopy (SIMS).

Analytical Techniques - Imaging

This section provides an overview of two imaging techniques used in materials characterization: Transmission Electron Microscopy (TEM) and Scanning Transmission Electron Microscopy (STEM). We discuss the basics behind the technique and some issues related to their operation and interpreting the images.

Analytical Techniques Quiz

Surface Photovoltage Technique

This section provides a brief introduction to the Surface Photovoltage Technique. We discuss how the technique is used to monitor for metal and ion contamination on wafers.

Secondary Ion Mass Spectroscopy

This section provides additional detail on Secondary Ion Mass Spectroscopy (SIMS). We discuss the types of SIMS analysis: including static and dynamic SIMS. We discuss the instrumentation, and how to interpret the results of a SIMS spectra. We also show SIMS element maps and depth profiles.

Time-Of-Flight Secondary Ion Mass Spectroscopy

This section provides additional detail on Time of Flight Secondary Ion Mass Spectroscopy (TOF-SIMS). We discuss its use as a method for identifying surface contamination. We discuss the instrumentation, and show TOF-SIMS element maps and depth profiles.

Electron Energy Loss Spectroscopy

This section provides additional detail on Electron Energy Loss Spectroscopy (EELS). We discuss its use in TEM materials characterization, the instrumentation, the spectra, how to interpret the spectra, and EELS dot maps.

Auger Electron Spectroscopy

This section provides additional detail on Auger Electron Spectroscopy (AES). We discuss direct spectrums, differential spectrums, depth profiling, and Field Emission AES.

Electron Backscatter Diffraction

This section provides additional information on Electron Backscatter Diffraction (EBSD). We discuss its use in examining metal structures, like copper metallization as well as copper in Through Silicon Vias (TSVs).

Transmission Electron Microscopy

This section provides additional information on Transmission Electron Microscopy (TEM). We discuss the transmission electron microscope sub-systems. We also discuss imaging modes in the TEM: parallel beam, electron energy loss, convergent beam, and x-ray dispersion. We also discuss related topics like Energy Filtered TEM (EF-TEM), Scanning TEM (STEM), and Off-Axis Electron Holography.

Energy-Dispersive X-Ray Spectroscopy

This section provides additional information on Energy Dispersive X-Ray Spectroscopy (EDS). We discuss the physics behind the technique as well as the instrumentation. We also spend time on issues with EDS like fluorescence peaks, pulse pileup rejection, escape peaks, absorption edges, and other sources of noise. We also show some examples of EDS spectra and dot maps, with their use in a failure analysis application.

Documents

Analytical Techniques

This discussion on analytical techniques covers such topics as transmission electron microscopy, energy dispersive spectroscopy, wavelength dispersive spectrometry, quantitative X-ray analysis, auger electron spectroscopy, depth profiling, and secondary ion mass spectroscopy.

Videos

TEM - Electron Beam Diffraction

This short video shows the use of Transmission Electron Microscopy (TEM) for diffraction. Diffraction imaging allows the analyst to gather information on the crystal structure of a sample.

TEM - Energy Dispersive X-Ray Spectroscopy

This short video shows the use of Energy Dispersive X-Ray Spectroscopy (EDS) on the Transmission Electron Microscope (TEM). EDS is not only a useful analytical tool on the SEM, but it also works well on the TEM, providing increased resolution.

TEM - Imaging

This short video shows the use of the Transmission Electron Microscope (TEM) to image the features on a CMOS IC at high magnification. Features like the barrier metals, gate oxide, and defects like an oxide undercut are clearly visible.

TEM - Sample Preparation

This video sequence summarizes the major steps for classical Transmission Electron Microscope (TEM) sample preparation. We show the grinding/polishing steps, the assembly of multiple slices into one sample, the punch operation, the additional thinning, and ion milling.

Energy Dispersive X-Ray Spectroscopy

This video shows the use of Energy Dispersive X-Ray Spectroscopy (EDS) on the Scanning Electron Microscope (SEM). We show the elements present in a packaged sample at the die/die attach interface through the use of spectra and x-ray dot maps.

Analysis - Package Level

Package Level Analysis

As semiconductor packaging becomes more complex, more analysis is required at the package level. There are several techniques that are used frequently for package level analysis. These include: acoustic microscopy, hermetic seal techniques, optical microscopy, particle impact noise detection (or PIND), and x-ray radiography. In addition to these non-destructive techniques, it is also necessary to have techniques to access or expose the die for further analysis. This access may be from the front side or the back side depending on the device and the information required.

Package Access

An important step in most analysis work is gaining access to the die surface or backside of the silicon. There are a wide variety of package styles and configurations, and as such, there are a variety of decapsulation techniques. This material covers decapsulation and sample preparation techniques for both frontside and backside analysis work.

Presentations

Decapsulation - Overview

Backside Sample Preparation - Part 1

This section covers a number of techniques used for decapping integrated circuits and semiconductor devices. It includes mechanical, chemical, and thermal techniques.

Backside Sample Preparation - Part 2

This section covers the use of mechanical grinding and polilshing as a backside sample preparation technique. It also covers the use of computer numerically-controlled milling, and reactive ion etching.

Backside Sample Preparation - Part 3

This section covers the use of the focused ion beam and laser microchemical technique for preparing local areas from the backside.

Quiz: Package Decapsulation and Backside Sample Preparation

Documents

Decapsulation/Backside Sample Preparation

Various methods of decapsulation and backside sample preparation are discussed here, including mechanical delidding and chemical delidding.

Videos

Laser Decapsulation

CNC Milling

Package Inspection Techniques

Introduction

Because the package can cover potential problems, one needs techniques for examining the package. These techniques fall into two categories: destructive and non-destructive. Destructive techniques involve removing material or puncturing a device cavity, while non-destructive techniques use electrical, x-ray, magnetic, or acoustic techniques to image structures or observe electrical behavior within the package.

Presentations

Package Inspection Techniques - Overview

This section covers the basics of plastic and ceramic packaging technologies. It includes a discussion of wirebonding, die attach, and package lead-frame construction.

Package Inspection Techniques - Part 2

This section covers the use of optical imaging for examination of package-related failures.

Package Inspection Techniques - Part 3

This section covers x-ray radiography and micro-focus x-ray imaging. This technique can identify packaging flaws, contamination, and voids.

Package Inspection Techniques - Part 4

This section covers scanning acoustic microscopy. This technique can identify interface problems and delaminations.

Package Inspection Techniques - Part 5

This section covers techniques used to evaluate package cavities. The techniques discussed include: hermetic seal testing, particle impact noise detection, and residual gas analysis.

Lock-In Thermography

Package Analysis Techniques Quiz

Documents

Packaging Testing

Here we talk about package-level testing, including external visual examination, X-ray radiography, hermeticity testing, fine leak hermetic seal testing, gross leak hermetic seal testing, particle impact noise detection testing, and acoustic microscopy.

Videos

CSAM Video Presentation

This video describes C-Mode Scanning Acoustic Microscopy (CSAM). We show how to set up the system, and acquire data on a plastic encapsulated integrated circuit.

X-Ray Microtomography Example

This video shows an example of how Computed Tomography (CT) imaging can improve one's ability to see information within a packaged device. In this example we show a Flip Chip Ball Grid Array (FC-BGA) package using CT X-Ray Microtomography. This technique allows one to see detail in 3 dimensions that might not otherwise have been visible, as well as look at cross-sectional information.

X-Ray Nanotomography Example

This video shows an example of how Computed Tomography (CT) imaging can improve one's ability to see information at the nanoscale using CT X-Ray Nanotomography. This technique allows one to see detail on an IC die in 3 dimensions that might not otherwise have been visible, as well as look at cross-sectional information.

Dage X-Ray

Acoustic Microscopy

Introduction

Scanning Acoustic Microscopy is an important technique used in failure analysis and quality inspection of semiconductor components. Scanning Acoustic Microscopy or (SAM), uses sound waves and their interactions with materials and materials interfaces to produce a waveform or image of the internal construction non-destructively. SAM primarily detects changes at interfaces, so these features are the primary ones in the image or waveform. Engineers use SAM to identify cracks, delaminations, voids, and placement of structures in complex packages.

Presentations

SAM - Equipment

This section discusses the equipment used for scanning acoustic microscopy. We discuss the various manufacturers, cover the block diagram of the system, and discuss the various transducers for generating and detecting the acoustic signals.

SAM - Imaging Modes

This section discusses the imaging modes used in scanning acoustic microscopy. We cover the main imaging modes like A-mode (spot), B-mode (line scan), C-mode (area scan), and TSAM (transmission area scan) along with some of the less well known modes like time-of-flight and QBAM.

SAM - Interpretation

This section covers how to interpret scanning acoustic microscope images. We show both waveforms and images and discuss the issues related to interpreting what the data means.

SAM - Physics of Operation

This section covers the physics behind scanning acoustic microscopy. We discuss transmission and reflection at interfaces, and discuss how the materials affect both transmission/reflection and phase inversion.

Quiz: Acoustic Microscopy

Documents

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Videos

Acoustic Microscopy

X-Ray Radiography

Introduction

X-Ray Radiography is an important non-destructive technique used not only for failure analysis but also for package inspection during the assembly process. In this course we cover the fundamentals of x-ray radiography, including how one generates and forms an x-ray image, the effects of materials on x-ray transmission. We also cover the equipment used for x-ray inspection, interpretation of x-ray images, and how one performs computed tomography (CT) imaging.

Presentations

X-Ray Radiography - Computed Tomography

This section introduces the topic of x-ray computed tomography. This technique allows the analyst to create a three-dimensional image of the component, much the same way a doctor would use computed tomography to create a three-dimensional image of a bone. This technique can facilitate cross-section views and even fly-through animations.

X-Ray Radiography - Equipment

This section describes the equipment used for x-ray radiography. We describe the x-ray source, the detector options, and the general equipment configurations.

X-Ray Radiography - Fundamentals

This section describes the fundamentals of x-ray radiography. We cover how x-rays generate contrast in materials, and describe the relationship between density, atomic number and x-ray stopping power.

X-Ray Radiography - Interpretation

This section describes how to interpret x-ray radiographs. This is particularly important for failure analysis work as well as MIL-STD inspection procedures. We discuss issues associated with roundness, angles, and what to do if an image is difficult to interpret.

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Videos

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Time Domain Reflectometry

Introduction

Time Domain Reflectometry (TDR) is a non-destructive technique used for package-level failure analysis. We use it to isolate opens or large changes in resistance within the package substrate, or connections between the substrate and die. TDR is also used for signal integrity verification in high-speed test. In this course we cover the basics of TDR, the equipment and setup, and how to interpret TDR signals. We also discuss the latest developments, including Electro-Optical TDR, which uses light pulses to provide better spatial resolution.

Presentations

Time Domain Reflectometry

This section describes Time Domain Reflectometry (TDR). TDR is an electrical technique used for localizing opens in packaged devices. We discuss the basic method, its limitations, and how to improve the resolution of the technique by using Electro-Optical TDR.

Quiz: Time Domain Reflectometry

Documents

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Videos

Time Domain Reflectometry

This video describes the basic Time Domain Reflectrometry (TDR) instrumentation and setup. We discuss how to acquire the data, and how to interpret the waveforms to estimate the location of an open circuit in packaged device.

Magnetic Field Imaging

Introduction

Magnetic Field Imaging (MFI) is a non-destructive technique used for localizing current paths within an integrated circuit. We also use the technique to isolate opens and resistive connections. In this course we cover the fundamental physics governing MFI, the equipment used to perform this work, gathering images, the differences between the different sensor types (Superconducting Quantum Interference Device (SQUID) and Giant Magnetoresistive (GMR) sensors), and how to interpret the images. We also discuss Space Domain Reflectometry and how it is used to localize opens.

Presentations

Magnetic Field Imaging

This section describes the physics behind Magnetic Field Imaging (MFI). We discuss the detectors, and how to generate the images using scanning methods.

Magnetic Field Imaging - Applications

This section covers several examples using the Magnetic Field Imaging (MFI) technique. We discuss how to identify short circuits, high resistance connections, as well as opens using a variant of MFI known as Space Domain Reflectometry.

Quiz: Magnetic Field Imaging

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Videos

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Chemistry Basics

Chemistry Basics Overview

Introduction

This section covers basic chemistry principles that are the foundation for semiconductor processing. It also provides an important foundation for semiconductor packaging technology. Chemistry also plays a big role in failure analysis deprocessing techniques.

Presentations

Balancing Chemical Equations

This section covers the procedure for balancing chemical equations.

Naming Compounds

Limiting Reactants Experiment

This video shows an experiment that demonstrates how to determine the limiting reactant in a reaction.

Balancing Chemical Equations Quiz

This quiz provides you an opportunity to see how well you have retained the concepts regarding balancing chemical equations.

Periodic Table

Interactive Periodic Table

Documents

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Videos

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Design

Design is an important aspect of semiconductor technology. Without circuit designs, we would not have the functionality that currently exists in our computers, automotive electronics, telecommunications, military systems, and consumer electronics. Design requires an understanding of theory, transistor operation, and higher level abstractions of functionality. It also requires competence with the tools that create these circuits.

Increasingly, design and manufacturing are interacting. This can be seen with the emphasis on Design for Manufacturing or Manufacturability (DFM). Although the Semitracks Online Training site is more focused on manufacturing issues, design plays and increasing role in production activities like test and yield, as well as in product engineering activities, like reliability and failure analysis.

This workspace is broken into two areas: Digital Fundamentals and Design. Digital Fundamentals covers topics on binary arithmetic, logic, and logic operators, while Design covers introductory courses on digital and analog design, as well as design validation.

Digital Fundamentals

Introduction

This course material covers fundamental concepts associated with digital circuit design. While many engineers who studied electrical engineering might be familiar with these concepts, those who studied physics, materials science, or another branch of engineering may not be familiar with these ideas. This content also serves as a good reference for those who studied these ideas, but need access to them for reference or to refresh their memories.

This section primarily concerns boolean algebra, logic notation, basic logic gates, truth tables, and methods for simplifying truth tables.

Presentations

Binary Number System

This presentation provides an introduction to the Binary Number System. The Binary Number System is the foundation of virtually all electronics data manipulation. It covers converting between the decimal and binary number systems, one's complement arithmetic and two's complement arithmetic.

Basic Logic Gates

This section covers the basic logic gates including: the inverter, AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR gate, and Exclusive-NOR gate. It also covers basic logic block construction.

Basic Logic Operators and Boolean Algebra

This section covers basic logic operators and functions and boolean algebra.

Logic Functions

This section describes how to create a logic function based on a truth table using a technique involving Karnaugh maps.

Quiz: Digital Fundamentals

Documents

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Videos

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Basic Design

Introduction

This material covers general topics in IC design. IC design is a broad category, and we'll be working to add more material into this course area. Right now, the system contains some basic presentations on design topics. It contains overview presentations on digital design, analog design, design validation, and other topics.

Presentations

TTL Design and Operation

This course explains the basic design of bipolar transistor-transistor-logic (TTL) gates and their operation.

Amplifiers and Multipliers

This section covers the basic design concepts behind CMOS amplifiers and multipliers. Topics covered include input stages, output circuits, feedback, and compensation.

Analog Circuit Basics

This section covers basic analog circuit elements including the transistor, current source, the cascode connection, and voltage reference circuits.

Design Validation

This section serves as a basic introduction to the concept of design validation. Design validation is becoming critical for today's complex ICs.

Dynamic Analog Circuits

This section covers several dynamic analog circuits including sample and hold circuits, voltage offset reduction circuits, switched capacitor integrators, and dynamic comparators.

Documents

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Videos

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Modeling

Introduction

This course material covers basic transistor behaviors and describes how to model them using a common modeling and simulation program called Matlab. Most engineers took courses on bipolar and MOS physics, but need to review the basic equations from time-to-time. However, there have not been good general tools to simulate transistor behavior as well as other circuit behaviors. Matlab is a tool that provides a calculation engine for graphing transistor performance, solving basic electrical circuit problems, and developing/analyzing more sophisticated designs. These materials, along with a student copy of Matlab, can provide not only a refresher on transistor modeling and simulation, but also an introduction to a powerful tool used extensively in circuit design today.

Presentations

Solving for an Unknown Voltage in a Circuit

This presentation shows how to use Matlab to solve for an unknown voltage in a circuit using Ohm's Law and Kirchoff's Law.

Solving for Two Unknown Currents in a Circuit

This presentation shows how to use Matlab to solve for two unknown currents in a circuit using Ohm's Law and Kirchoff's Law. In this section, we introduce the use of a matrix to solve for the unknowns.

Solving for Multiple Unknown Currents and Voltages in a Circuit

This presentation shows how to use Matlab to solve for multiple unknown voltages and current in a circuit using Ohm's Law and Kirchoff's Law. In this section, we use a five by five matrix to solve for the unknowns.

Bipolar Junction Transistors - Basic Equations

This presentation reviews the basic bipolar transistor equations and describes how to plot the emitter current as a function of the base-emitter voltage using Matlab.

Bipolar Junction Transistors - IC Versus VCE

This presentation demonstrates how to set up and plot the collector current as a function of the collector-emitter voltage with a fixed base-emitter voltage for a bipolar junction transistor using Matlab.

Documents

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Videos

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Interface Circuits

Introduction

This course discusses interface circuits and technologies for sending and receiving signals to and from the die. Currently, this course contains information on the Inter-Integrated Circuit (I2C) interface, but will be populated with information on a number of additional interface circuits, like: the Serial Peripheral Interface (SPI), Low Voltage Differential Signaling (LVDS), the Universal Serial Bus (USB), and others.

Presentations

I2C Interface

This section briefly covers the Inter Integrated Circuit, or I2C specification. This circuitry was traditionally used for chip-to-chip communication on printed circuit boards in the early days of the personal computer. Today it is also used as a test interface for some types of analog integrated circuits.

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Device Physics

Device physics is fundamental to semiconductor technology in a number of ways. It is necessary to understand the behavior of transistors, both from a qualitative standpoint as well as from a more-detailed modeling standpoint. Device physics provides the basis for technology development. The path from junctions to bipolar junction transistors to MOSFETs to compound semiconductors relies on an in-depth understanding of device physics. Device physics also serves as the basis for understanding chip design and layout issues, fab processing issues, reliability physics issues, and analysis and characterization issues. While most engineers study this field in college, it is always good to review this topic and understand new developments in this area. This workspace provides that review and understanding necessary for semiconductor devices and integrated circuits.

Device Physics Basics

Introduction

This course provides an introduction to device physics from a visual perspective. Device physics can be difficult to understand if one tries to delve into the complex mathematics associated with solid state and semiconductor behavior. A much easier way to understand device physics is to visualize the concepts. We work through the major concepts using images and animations to give the user an intuitive perspective of the subject.

Presentations

Junction and Depletion Regions

Semiconductors and Carriers

Documents

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Videos

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Semiconductor Junctions

Introduction

This material covers the basic device physics associated with semiconductor junctions. The material details the pn junction and its behavior.

Presentations

Silicon Properties

This section provides an introduction to silicon properties that are important to semiconductor fabrication. It includes material on Fermi Level and energy band diagrams. The material discusses the Fermi potential, drift, current density, conductivity and resistivity of silicon, carrier transport, mobility and scattering mechanisms as well as Matthiessen's rule. The section also covers transitions due to energy states within the silicon due to doping and impurities and ends with a discussion on minority carrier diffusion length.

PN Junctions and Diodes

This section covers the basic device physics for silicon pn junctions and diodes. It includes information on topics such as built-in voltage, depletion width, carrier behavior in forward and reverse bias junctions, generation, recombination, impact ionization, and breakdown voltages. There is also information on zener diodes and P-I-N diodes.

Contacts

This section covers the basic device physics for metal to silicon contacts. It includes details on rectifying contacts, ohmic contacts, and the Schottky barrier diode.

Documents

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Videos

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MOSFETs

Introduction

This material covers the device physics associated with the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The material details the role of the dielectric gate and junctions and their behavior. We cover topics like inversion, accumulation, depletion, active region, sub-threshold region, and more.

Presentations

Dielectric Physics

This section delves into the physics of the metal-oxide-semiconductor (MOS) dielectric material. It describes the concept of effective oxide thickness, introduces the topic of a capacitance-voltage (CV) plot, charge pumping, and describes charge and trapping mechanisms. It includes information on interface trap charge, mobile ion charge, and oxide trapped charge.

FET Device Physics

This section covers the basic properties of the p- and n-channel MOSFET. It includes discussion on the band structure, accumulation, depletion, flatband, weak inversion, strong inversion, surface potential, surface charge, and how to intepret C/V plots.

MOSFET Basics

This section covers the basic operation of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). It covers the equations that cover the fundamental operation of the MOSFET. It includes the simplified linear current relation, saturation mode and the basic equations in this regime, subthreshold leakage, mobility and its degradation, threshold voltage, effective channel length, resistances, and the body effect.

CV Plotting

This section describes how to perform a capacitance-voltage (CV) plot and interpret the data. CV plotting can provide information on transistor behavior in depletion, inversion, and accumulation, as well as provide information on ionic contamination.

Circuit Elements

This section covers basic circuit elements used in MOS devices. These include inverters, and memory structures such as DRAM cells (both stacked capacitor and trench capacitor)

Documents

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Videos

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Bipolar Transistors

Introduction

This material covers the device physics associated with the bipolar junction transistor. The material details the role of the collector, base, and emitter. We cover topics like gain, Early voltage, the Kirk effect, and more.

Presentations

Bipolar Transistor Basics

Bipolar Transistor Behavior

This section covers the basic operation of the bipolar transistor. It describes the basic regimes of operation, include forward bias, the current-voltage relationship, emitter efficiency and transconductance. It describes a classical transistor structure, and more modern bipolar transistor structures.

Bipolar Transistors - Tradeoffs and Effects

This section covers issues associated with modern bipolar transistors and techniques for dealing with them. This includes discussions on the Early voltage, concentration effects in the emitter, current gain variations, current crowding effects, the Kirk effect, transistor speed, flicker noise (1/f), and breakdown voltages.

Bipolar Enhancement Techniques

This section covers techniques to improve the performance of bipolar transistors. It focuses mainly on polysilicon emitters for better junction control, silicon-germanium (SiGe) material substitution in the base region to improve mobility and transit times, and silicon-germanium-carbon (SiGe:C) to control transient enhanced diffusion effects.

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Videos

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Failure Analysis - Procedures

Failure Analysis requires semiconductor design and processing knowledge, logical thinking, and detective skills. In many respects, the job of failure analyst is much like the job of a detective. The failure analyst must search for clues and evidence as to what might have caused the circuit to fail the way it did. Each and every clue that the analyst uncovers (through testing or examination) may potentially be important. This requires that the analyst be organized and develop a story that makes sense. In other words, the failure mechanism found must correlate to the observed failure mode.

There are also several guiding practical principles when performing failure analysis. The first and most important principle is to understand what detail of analysis is required by your customer. This is important for two reasons. One reason is that we do not want to perform extra work if it is not necessary. Performing an in-depth, detailed analysis may not be necessary if all the customer want to know is whether or not he or she damaged the device. The second reason is that we do want to take extra care and precaution for a critical failure. For example, if the device we are analyzing is suspected to have caused the failure of a satellite launch, we will want to take extra care and perform the analysis in a great amount of detail.

Being able to understand what techniques to perform in what order is the hallmark of a mature product analyst. Determining what techniques to perform and what tests to run require both knowledge of the techniques and philosophy behind failure analysis, as well as an understanding of the product to be analyzed. To learn more about this topic, examine the materials in this workspace.

Principles and Procedures

Introduction

This material covers the principles and procedures that are used to guide the analyst through the failure analysis process. It includes topics on high level analysis flow, and specific topics like interpreting damage. This material also includes flowcharts on a variety of topics.

Presentations

Interpreting Overstress Damage

This section provides information to the analyst on how to interpret the difference between electrical overstress and electrostatic discharge as well as determine pulse width and amplitude.

Principles and Procedures - Part 1

This section covers some basic information regarding the evolution of failure analysis over the past 40 years. It also lists the basic philosophical and practical principles associated with failure analysis.

Principles and Procedures - Part 2

This section covers the top level flowcharts associated with both packaged part failure analysis and wafer or die level yield analysis.

Principles and Procedures - Part 3

This section covers the second level flowcharts associated with particular activities such as electrical characterization, package characterization, fault isolation at the chip level, defect localization at the gate/interconnect level, and materials characterization.

Quiz: Principles and Procedures

This quiz reviews the basic concepts associated with the philosophy, practical rules, and procedures of failure analysis.

Principles and Procedures - Part I (Japanese)

This material covers the principles and procedures that are used to guide the analyst through the failure analysis process. It includes topics on high level analysis flow, and specific topics like interpreting damage. This material also includes flowcharts on a variety of topics.

Documents

Principles and Procedures

The principles and procedures of failure analysis are discussed, including product top-level analysis flowcharts, second-tier flowcharts, and analysis and technique orders.

Videos

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Gathering Information

Introduction

Gathering background information is a critical part of any failure analysis effort. Having the proper information and history on a failure can make an analysis run smoothly and avoid costly and time-consuming mistakes. This material covers the type of background information that should be gathered for an analysis.

Presentations

Gathering Background Information

This section describes the process an analyst should use to collect the necessary and salient information to perform the failure analysis efficiently.

Documents

Gathering Information

This short chapter talks about what information is necessary for failure analysis and how to obtain it.

Videos

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FA Case Histories

Introduction

This material covers the overall process of a Failure Analysis effort from beginning to end. The idea is to understand how FA principles and procedures determine which techniques to use, and how one can isolate down to the failure mechanism, then determine the root cause, and then recommend corrective action. We provide several Case Histories for the user to test their skills determining the correct path for an analysis.

Presentations

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Documents

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Simulations

Failure Analysis Case Histories

This case history covers several integrated circuit failures that were observed at electrical test after packaging.

Final Test

Introduction

This is the final test for failure analysis. It must be completed with a passing grade (70% or greater) in order to receive a certificate in failure analysis.

Presentations

FA Final Test

Documents

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Simulations

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Failure Mechanisms

Introduction

Failures, although unwanted, are necessary to understand in detail in order to manufacture, package, and field semiconductor components and electronic systems. Failure mechanisms fall into four broad categories:

  • Dielectric Failure Mechanisms
  • Diffusion and Bulk Defects
  • Interconnect Failure Mechanisms
  • Package Level Failure Mechanisms
  • Transistor Failure Mechanisms
  • Use Condition Failure Mechanisms

This material describes a number of failure mechanisms in detail, providing a basis for the student understand how they occur, the physics that drive the mechanisms, their reliability impact (if any), and techniques or methods to mitigate them.

Presentations

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Documents

Electromigration

In this chapter we introduce the basics of electromigration, failure distributions, and ways to improve electromigration performance. Topics include: physical characteristics of metal films, mathematical models of electromigration, Blech effect, Blech length, Black's equation, and electromigration failure distributions.

EOS/ESD

In this chapter we talk about electrical overstress and electrostatic discharge. Topics include: electrical overstress, electrostatic discharge, sources of ESD, reliability implications, mitigation techniques, latch-up, initiation, testing, mitigation techniques, and snapback.

Hot Carrier Effects

Here we take a look at hot carrier injection mechanisms and the physical effects on circuits associated with them. Topics include: hot carrier injection mechanisms, effects on logic circuits, effects on memory circuits, deep submicron effects, negative bias temperature instability, mitigation techniques, deuterium anneal, and AC hot carrier effects.

Ionic Contamination

This section discusses ionic contamination. It talks about the effects of contamination and the methods for controlling it.

Moisture

In this chapter we talk about external package corrosion, inter-planar leakage, die-level moisture related mechanisms, and modeling moisture transport in plastic.

Radiation Damage

Here we look at sources of radiation, the effects it can have, and ways to minimize those effects.

Stress Induced Voiding

In this chapter we inspect the physics of stress induced voiding, including it's three main components: the driving force, nucleation point, and means to grow.

Thermal Degradation

In this chapter on thermal degradation, we look at intermetallic formation and the thermal degradation of lead finish.

Thermomechanical Stress

Covered in this chapter are several failure mechanisms, including die cracking in ceramic packages, die cracking in plastic packages, plastic package cracking and popcorning, bond wire damage, thin film cracking, and accelerating thermomechanical stress.

Time Dependent Dielectric Breakdown

Here we examine several aspects of breakdown, including Fowler-Nordeim tunneling, direct tunneling, trap assisted tunneling, bandgap ionization model, classic anode hole injection model, hydrogen release model, thermochemical model, accelerated stress testing, voltage ramp, current ramp test, AC effects, and extrinsic breakdown.

Videos

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Package Level Failure Mechanisms

Introduction

This section covers reliability failure mechanisms in semiconductor components that are related to the package, or package and assembly process. It can be grouped into several categories: moisture and contamination, thermal degradation, and thermomechanical stress. Moisture and contamination contributes to a class of failure mechanisms. Moisture, in combination with certain materials, can lead to leakage and/or corrosion. Thermal degradation is a specific mechanism that falls into a broader category of thermal degradation. This mechanism is activated solely by temperature, although some researchers have observed that catalysts like Bromine or Humidity can influence the rate of failure. Intermetallic degradation usually results in voiding, that weakens the bond, eventually leading to elevated resistance, intermittent operation, or open circuits. Thermomechanical stress arises from the mismatch of coefficients of thermal expansion in the materials in the package. This can lead to specific problems like package cracking, die cracking, popcorning, bondpad cratering, and bond wire tensile breaks.

Presentations

Moisture and Corrosion

Moisture represents a significant threat to semiconductor reliability. A number of materials used in the semiconductor manufacturing and packaging processes can react with moisture (or moisture and an electric potential) and corrode. This section discusses this reliability mechanism.

Thermal Degradation

Thermal degradation is a class of failure mechanisms that result in materials problems. At elevated temperatures some alloys can form that can have detrimental effects on the physical and/or electrical properties of a semiconductor component. Examples of this type of failure mechanism include intermetallic formation, or purple plague, and lead finish degradation.

Thermomechanical Stress - Part 1

Thermomechanical stress is a group of failure mechanisms that are caused by the combination of mismatches in coefficients of thermal expansion between materials in the semiconductor component and thermal cycling or thermal excursions. These mechanisms include stresses to the bond wires, interactions between the die surface and the plastic encapsulating material, and stresses to the die itself.

Thermomechanical Stress - Part 2

Thermomechanical stress is a group of failure mechanisms that are caused by the combination of mismatches in coefficients of thermal expansion between materials in the semiconductor component and thermal cycling or thermal excursions. These mechanisms include stresses to the bond wires, interactions between the die surface and the plastic encapsulating material, and stresses to the die itself.

Documents

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Videos

Bond Shear Video

Wire Pull Test

Diffusion and Bulk Defects

Introduction

This material covers diffusion and bulk defects. Diffusion and bulk defects are defects that occur in the semiconductor material. They can be caused by contamination, improper processing, stress, and other events. Although these defects can result in yield loss and marginal operation, they rarely pose a reliability risk, because the temperatures required to cause their behavior to change is quite high.

This material is further broken down into diffusion alignment problems, diffusion profile anomalies, masking defects, under/over-sized mask features, and crystal defects. For more information, click on the topic of interest to view a short presentation on the subject.

Presentations

Diffusion Alignment Defects

This section covers diffusion alignment defects.

Diffusion Profile Anomalies

This section covers diffusion profile anomalies.

Random Diffusion Masking Defects

This section covers random diffusion masking defects.

Under or Oversized Masking Features

This section covers under/over-sized masking features.

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Dielectric Failure Mechanisms

Introduction

This material covers dielectric failure mechanisms. This includes the dielectrics used for the transistor gates and the dielectrics used to isolate the interconnect. Dielectric breakdown is a common failure mechanism and has been studied for many years by scientists and engineers. Dielectric breakdown affects the transistor gates. It can lead to increased leakage, reduced performance, or functional failures. Gate oxide breakdown can be the result of extrinsic items, like contamination or surface roughness, or can be time-dependent degradation of the oxide itself. This mechanism is activated by several factors. In thicker oxides electric field, temperature, and even energetic electrons and holes can lead to breakdown. In thinner oxides, the voltage across the oxide is the more predominant factor. This material represents the latest thinking on dielectric breakdown.

Presentations

High-K Gate Dielectric Reliability

This section discusses the reliability issues associated with the new high dielectric constant materials used for transistor gates.

Time Dependent Dielectric Breakdown Overview

Time-Dependent Dielectric Breakdown, or TDDB as it is also known, is a mechanism that degrades thin oxides subjected to high electric fields. A high electric field stresses an oxide, producing damage in the form of traps. These traps can eventually cause increased leakage. Sufficient leakage can result in dielectric breakdown.

TDDB - Introduction

This section provides an overview of the current state-of-the-art issues associated with oxide reliability. Specifically, the section covers the thin oxides used for gate dielectrics and tunnel dielectrics.

TDDB - Soft Breakdown

This presentation covers the relatively new phenomenon of soft breakdown. Soft breakdown does not immediately render the transistor non-functional, so one must understand the phenomenon in detail. It includes material on how to model soft breakdown events, and how to estimate time-to-failure.

TDDB - Oxide Properties

TDDB - Oxide Breakdown Models

This section covers the most up-to-date thinking regarding oxide breakdown. The most current models based on voltage, electric field, carriers and the power law are covered.

TDDB in Copper Low-K Systems

This section covers time-dependent dielectric breakdown in back-end dielectric materials. It includes material on models, copper migration, barrier layer, capping layer, and other effects.

Time Dependent Dielectric Breakdown Quiz

This quiz covers the Time Dependent Dielectric Breakdown (TDDB) mechanism.

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Interconnect Failure Mechanisms

Introduction

This material covers failures that occur in the IC interconnect system. Metallization failure is another topic that has been studied for many years by scientists. Metallization failures are common in integrated circuits and can occur because of stress or electromigration, as well as other mechanisms. This material represents the most current thinking regarding both electromigration, and stress voiding. Electromigration is the movement of atoms under high current densities. This mechanism is accelerated by temperature and current, and is also quite dependent on the grain structure and interfaces that surround the copper interconnect. This mechanism can lead to increased resistance or opens in lines, or in some cases, even shorts between adjacent lines. Copper electromigration is mitigated through design techniques to minimize current densities and through technological means by ensuring good interfaces between the copper metal and the surround seed and capping layers.

Presentations

Electromigration in Copper Low-k Systems

This section discusses electromigration as it applies to copper interconnect systems. We discuss the effects of liners, etch stop layers, CMP effects, copper alloying, and copper deposition conditions.

Electromigration Quiz

This quiz covers the user's knowledge of electromigration.

Stress Induced Voiding

This presentation covers the basic concept of stress induced voiding. We cover the physical mechanism and the main model used to understand this mechanism.

Stress Induced Voiding - Model

Stress Induced Voiding in IC Interconnects

Stress Induced Voiding - Case History

This presentation covers an example of stress voiding, how it was discovered and identified, and how it was eliminated from the process.

Stress Induced Voiding in Current Technologies

This section covers stress migration/stress induced voiding in copper metallization systems. It addresses the effects of barrier layers, vias, grain size, alloying, and other issues specific to copper and low-k dielectrics.

Stress Induced Voiding Quiz

This quiz tests the student's knowledge of Stress Induced Voiding.

Electromigration Overview

This section provides an overview of electromigration. We describe the basic mechanisms and discuss Black's law for modeling the phenomenon. We also discuss analysis techniques for electromigration, and sources of the problem from both a design and processing perspective.

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Transistor Failure Mechanisms

Introduction

This material covers reliability failure mechanisms in semiconductor components that are related to the transistor behavior. These mechanisms fall into several categories: hot carrier effects (HC), ionic contamination, and negative bias temperature instability (NBTI). Some mechanisms are well understood, like ionic contamination, while mechanism like NBTI are still poorly understood. This material represents the latest thinking on these mechanisms. Negative Bias Temperature Instability affects p-channel transistors. The charge build-up in the oxide and at the interface leads to degradation of the performance of the transistor, which in turn degrades the performance of the chip. This mechanism is accelerated by both temperature and the gate voltage. Currently, there are no good technological solutions to reducing NBTI, so engineers address this problem through design with lower voltages and appropriate switching architectures.

Presentations

Hi-K PBTI

This section provides an introduction to high dielectric constant gate materials, or high-k gates, and their failure mechanisms. It discusses issues associated with processing order (gate first, or gate last). It introduces the major failure mechanism which is fast trapping, and discusses the need for fast measurement techniques. It also discusses methods to improve the dielectric reliability, like fluorinated gates.

Hot Carrier Degradation - Overview

This section talks about the historical failure mechanism known as hot carrier degradation. It describes how it occurs, and the techniques used to mitigate its effects. Today, hot carrier effects are largely contained by scaling the voltage on the IC.

Hot Carrier Degradation - Device Effects

Hot Carrier Degradation - Physics

Hot Carrier Degradation Quiz

This quiz covers hot carrier degradation.

Ionic Contamination

This section talks about the historical failure mechanism known as ionic contamination. It is largely contained today by aggressively controlling cleanliness in the fab, removing human handling, and using ultra-pure chemicals. This section covers the major technological approaches for reducing ionic contamination is the circuit as well.

Negative Bias Temperature Instability

This section covers Negative Bias Temperature Instability (NBTI), its effects on transistors and circuits, and how to characterize the mechanism.

NBTI Quiz

This quiz tests the student's knowledge of Negative Bias Temperature Instability.

Documents

Hot Carrier Degradation

Videos

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Use Condition Failure Mechanisms

Introduction

This section covers reliability failure mechanisms in semiconductor components that are related to use conditions or the environment. It can be grouped into two main categories: electrical overstress/electrostatic discharge and radiation effects. Other overstress subjects like latchup and snapback are also covered in this material.

Presentations

Electrical Overstress and ESD

Overstress and ESD are common system-level problems that can affect semiconductor devices. There are four major overstress mechanisms: gross overstress, electrostatic discharge (ESD), latch-up, and snapback.

Interpreting Overstress Damage

This section provides information to the analyst on how to interpret the difference between electrical overstress and electrostatic discharge as well as determine pulse width and amplitude.

Radiation Effects

Radiation effects are a growing concern in many microelectronic devices. The most common radiation effect is the Single Event Upset or SEU. This can cause temporary errors in memories and logic path corruption in microprocessors. Another effect is charge build-up in oxides that can result in performance degradation.

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MIL-STD Training

Introduction

Military Standard (MIL-STD) procedures dictate that various activities require trained operators. The standards of primary interest for this area are MIL-STD 883 and MIL-STD 750. This classroom contains courses on these topics. Right now, we have a course on Pre-Cap Visual Inspection loaded into this system. As we deliver courses on other MIL-STD topics, we will add them to this classroom.

Pre-Cap Visual Inspection

Introduction

One major activity that requires operator training for companies dealing with military components is Pre-Cap Visual Inspection. This is the inspection performed before sealing the lid onto a hermetically-sealed component. Operators must be trained to recognize defects that could later cause failure of the component. This course covers how to perform the inspection, what constitutes a potential defect, and the taxonomy of possible problems. We also provide tests to determine your skills once you have completed the training.

Presentations

Introduction and Overview

This presentation describes Pre-Cap Visual Inspection and its application to high reliability components. It discusses the history, documentation, advantages, and disadvantages of the methodology.

Internal Visual Inspection for ICs - Part 1

This section introduces MIL-STD 883 Method 2010 for Internal Visual Inspection. It covers the purpose of the document, the basic inspection technique, and the equipment used for the inspection. It also provides a list of terms and definitions used in the inspection method.

Internal Visual Inspection for ICs - Part 2

This section covers the metallization portion of MIL-STD 883 Method 2010. It covers inspection for metallization scratches and voids, as well as corrosion, bridging, alignment, and coverage in vias and contacts. It provides the pass/fail criteria for various conditions and anomalies that an inspector might encounter.

Internal Visual Inspection for ICs - Part 3

This section covers the diffusion, scribeline, and thin film resistor portion of MIL-STD 883 Method 2010. It covers diffusion, passivation, glassivation, and dielectric faults, scribing and die defects, including chip-outs, cracks and voids, and anomalies with thin film resistors.

Internal Visual Inspection for ICs - Part 4

This section covers wirebonds and solder bumps inspection as called out in MIL-STD 883 Method 2010. It covers wirebond placement, aspect ratios, defects in the wire, wire cross-over criteria, rebond attempts, and solder bump placement and size.

Internal Visual Inspection for ICs - Part 5

The final section of MIL-STD 883 Method 2010 covers die mounting (epoxy and eutectic) anomalies, beam lead construction, foreign material, and backside metallization anomalies.

Equipment for Pre-Cap Inspection

This presentation describes the equipment used for Pre-Cap Visual Inspection. This includes optical microscopy, camera technology, and ESD workspaces.

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Packaging Design

Introduction

This material covers the electrical behavior, thermal properties, and the structural and mechanical aspects of electronic packaging. As packaging technology increases in complexity, a whole host of electrical, thermal, and mechanical issues must be accounted for and modeled. The electrical issues include resistance, capacitance, cross talk issues, power and ground bus disturbances, and high frequency packaging. Thermal issues include heat dissipation, the uses of ceramic and plastic, actively cooled packages, heat sinks and planes, and materials issues. Mechanical include thermal coefficient of expansion issues, plastic vs. ceramic packaging, as well as soldering issues. This material also covers the modeling techniques used to characterize these issues.

Presentations

Introduction to Packaging Modeling and Simulation

This section provides an introduction to the topic of Packaging Modeling and Simulation. It briefly covers the history of modeling and simulation, covers the types of modeling efforts used in the semiconductor industry, and describes the basic process.

Course and Instructor Overview

This presentation provides an overview of the Packaging Design and Modeling Course and an gives some background information on our Packaging Design expert, Steve Groothuis.

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Assembly Process

Introduction

This section contains an overview of the assembly process as well as some more detailed presentations on the assembly process. The assembly process normally includes such steps as Wafer Dicing, Die Attach to the Leadframe, the Wirebonding Process, the Mold Injection Process, Singulation, Trim and Form, and for Ball Grid Array (BGA) devices, the Redistribution Layer and Bump (sometimes just simplified as "Bump") Process.

Presentations

Assembly and Packaging Processes Introduction

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Packaging Elements

Introduction

Packaging elements includes information on the individual materials and structures used in semiconductor packages. This includes packaging elements like the leadframes, mold compounds, substrates, interposers, solder balls, copper pillars, and redistribution layers. We discuss each of these topics in more detail.

Presentations

Transfer Molding

This section covers the molding process used for semiconductor packaging. We include information on the overall process, the equipment and materials used for transfer molding, and the materials properties. We also describe characterization techniques, and modeling and simulation approaches. Finally, we discuss future materials for molding processes.

Through Silicon Vias

This section provides an introduction to Through-Silicon Vias (TSVs). The material covers both polysilicon and copper TSV technologies. It also includes information on stress and mobility issues, silicon stress, and electrical integrity. We also present information on TSV Parasitic models and bonding techniques.

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Package Types

Introduction

Packaging is one of the most active areas for development in the semiconductor industry right now. Someone recently estimated that there are more than 40,000 different package types currently on the market. In this course we will cover the more common package type families. These include: Standard Leaded Packages, Flip Chip Packages, Chip Scale Packages, Wafer Level Packages, Stacked Die Packages and Stacked Packages.

Presentations

Package Types

This section describes basic package types. Some of these package types have been in use for several decades. This includes leaded packages, ball grid array (BGA) packages, flip-chip packages, pin grid array (PGA) packages, leadless chip carrier (LCC) packages, and land grid arrays. This section covers both ceramic and plastic versions of these packages.

Flip Chip Packages

This section provides a brief overview of flip chip devices. These are circuits mounted such that the active transistors are face down with respect to the package connections. Typically, special materials are needed to make the connections between the bondpads on the die and the solder bumps. Flip chip devices may also utilize substrates or redistribution layers to expand the footprint of the connections to allow contact to the printed circuit board.

Chip Scale Packages

This section provides a brief overview of chip scale packages. Chip scale packages are packages that just exceed the size of the semiconductor die and are typically used in systems where space is at a premium, like mobile devices.

Wafer Level Packages

This section provides an introduction to wafer-level packages. A wafer-level package is a package where the package interconnect is produced as part of the wafer fabrication process. Wafer-level packages are used extensively by the memory manufacturers to reduce space and increase density for portable applications. Wafer-level packaging includes redistribution layer and bump process.

Stacked Die Packages

This section introduces stacked die packages, or packages with two or more die placed one on top of the other. It also briefly introduces the stacked package, or components with two or more packages placed on top of one another.

Stacked Packages

This section provides a brief overview to stacked packages. Stacked packages are packages where individual packages are designed in such a way to allow placement on top of one another. This type of package technology is relatively new and is needed for applications where space is constrained, like mobile devices.

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Packaging Design Concepts

Introduction

Today's packages can have significant interactions with the die, so some thought is required when designing a new package. This course covers some of those topics. We begin with some high-level package design principles. Basically, the package is used for electrical connections between the die and the system, removing heat, mechanical integrity, to protect the die from damage, to create a format that can be used by the electronics manufacturer. In advanced ICs, engineers actually design the package at the same time as the die, an activity known as chip-package co-design, and this topic is discussed here as well.

Presentations

Package Design Principles

This section provides an introduction to the packaging design process. Package design involves knowledge from several disciplines, including electrical engineering, mechanical engineering, industrical engineering, and materials science. This section briefly explains the activities performed by the package design engineer and tools used by the package design engineer.

Chip and Package Co-Design

This section provides a brief overview of the issues associated the chip and package design process. Since there are a number of interactions between the chip design and the package design process, engineers require tools for "co-design" or simultaneous design, to perform tradeoffs and optimize the component.

Solid Mechanics Concepts

This section describes materials properties and concepts that are important for design and modeling of packages. This includes properties like elastic modulus, Poisson's ratio, density, stain, stress, and CTE, along with descriptions of Hooke's law Saint Venant's principle, and a description of why packages tend to warp.

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Packaging Drivers

Introduction

Like much of the semiconductor industry, the semiconductor package developments come out of a number of drivers. The biggest drivers include cost, weight and size. Many of these drivers are captured by the International Technology Roadmap for Semiconductors (ITRS). Other drivers include manufacturability and reliability. These drivers are captured in part by the Joint Electron Device Engineering Council (JEDEC). JEDEC creates standards around package manufacturability and reliability, and we discuss that in this course.

Presentations

Packaging Business Issues

This section provides an introduction to the packaging design process. Package design involves knowledge from several disciplines, including electrical engineering, mechanical engineering, industrical engineering, and materials science. This section briefly explains the activities performed by the package design engineer and tools used by the package design engineer.

Packaging Engineering and the Electronics Ecosystem

This presentation describes the function of Packaging Engineering and discusses the various disciplines involved in packaging, including mechanical engineering, materials engineering, electrical engineering, and industrial engineering. It also discusses the role of Packaging Engineering in the broader context of the electronics ecosystem.

The ITRS and Its Impact on Packaging Design and Modeling

This presentation describes the International Technology Roadmap for Semiconductors (ITRS) and discusses the portions of the roadmap that apply to packaging design, modeling and simulation.

JEDEC Packaging Standards

This presentation describes the Joint Electron Device Engineering Council (JEDEC) and the industry standards related to packaging design and the various package configurations.

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Videos

Introduction

These videos and animations show the basic construction process for various package types. These are not meant to be detailed, but rather show the major, or high-level steps required for the various packaging technologies.

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Videos

Ceramic Dual Inline Package Animation

This brief animation shows a ceramic dual inline package from different angles with and without the lid.

Chip Scale Package

Lead-On Chip Package Animation

This brief animation shows the lead-on-chip package animation from different angles with and without the lead frame exposed.

MicroBGA: Lead Frame Preparation

This animation describes the lead frame preparation process for a micro Ball Grid Array (BGA) package.

MicroBGA: MF-LOC

This animation describes the assembly process for a multiframe lead-over-chip (MF-LOC) package.

MicroBGA: QFN

This animation describes the assembly process for a Quad Flat No-Lead (QFN) device.

MicroBGA: Solder Bump Formation

This short animation describes the solder bump formation process for a Micro Ball Grid Array (BGA) package.

MicroBGA: Terminal Formation

This short animation describes how terminals are formed for MicroBall Grid Array (BGA) and Quad Flat No-Lead (QFN) packages.

MicroBGA: Plastic Dual Inline Package Animation

This brief animation shows a plastic dual inline package with and without the die exposed.

Solder Bump Animation

This brief animation describes two methods for forming solder bumps using micropunching technology, the direct method, and the plate transfer method.

Packaging Technology

Introduction

Semiconductor packaging is becoming increasingly challenging. As integrated circuits increase in performance, new packaging techniques are required to remove the heat, handle the increased number of bondpads, and deal with the fragile Lo-K dielectrics used on these circuits. New technologies such as optoelectronics and microelectromechanical systems (MEMS) can require specialized packages. Smaller form factors require engineers to use higher density packaging options, like array packaging, chip scale packaging, and multi-chip modules. Although packaging can be a challenge, it can also provide a lower cost path for integration needs. For example, a system in a package design can be more cost effective than a system on a chip design. This section covers packaging technology issues, packaging design and modeling issues, as well as packaging reliability challenges.

Wafer-Related Activities

Although we think of packaging as primarily an activity separate from the wafer itself, there are some wafer-related activities one typically performs with certain assembly flows and package types. For instance, it is quite common to backgrind, or thin, a wafer prior to packaging it. This is common for today's thin profile packages. Another common wafer-related activity is the redistribution layer and bump sequence. This is also performed at the wafer level prior to sawing the wafer apart. Even the wafer sawing operation can be thought of as a wafer-level activity.

Presentations

Wafer Backgrinding/Thinning

Bump Processes

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Business Trends and Drivers

This section covers the business environment and the technical drivers that affect semiconductor packaging. The relentless pursuit of Moores Law by the semiconductor industry, the proliferation of packaging formats, and the introduction of new materials, have made packaging technology challenging in recent years. This section also provides an overview of these issues, and other issues, such as the rise of the system in a package (SIP) approach.

Presentations

Business Trends and Drivers

This section covers the semiconductor industry trends and drivers that affect the packaging community. We discuss the impact of Moore’s Law, consumer electronics and its requirement for low cost, low power, and small package footprints.

ITRS Roadmap

This section describes the packaging issues and needs that arise from the requipmenets of the International Technology Roadmap for Semiconductors (ITRS).

Assembly and Packaging Processes Introduction

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Videos

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Lead Free Issues

Lead-free electronics is fast becoming a reality. The pressure from the European Union, Japanese, and other legislative bodies almost guarantees that the industry will completely convert in the next several years. Right now, many manufacturers are using their lead-free components as a differentiator in the marketplace. The key challenges to going lead-free are technical and logistical in nature. On the technical side, the new solder alloys must be characterized for reliability performance. The surrounding materials must be able to withstand the higher reflow temperatures as well. On the logistics side, the conversion coordination will require a good deal of effort, since this involves schedules, supply lines, manufacturing processes, and other items. This section covers these issues in further detail.

Presentations

Lead Free Issues

Because of governmental directives, the electronics industry is moving away from lead-based solders to lead-free solders. Although lead-free solders can work to connect components to printed circuit boards, there are some issues. Lead-free solders have different properties than leaded solders, requiring different reflow temperatures, different flux materials, and new reliability characterizations. This section discusses these issues in more detail.

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System-on-a-Chip vs. System-in-a-Package

This material covers issues related to System on a Chip (SoC) and System in a Package (SiP). Both technologies have their advantages and disadvantages.

Presentations

System-on-a-Chip vs. System-in-a-Package

This section describes System-on-a-Chip (SOC) and System-in-a-Package (SIP) integration approaches. It highlights the advantages and disadvantages of each one.

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Use Conditions

As the complexity of electronics increases, it is becoming more difficult to use a one size fits all approach to reliability and qualification. Instead, most manufacturers now use a market segmentation approach that takes into account the use conditions of a component. Different environments require different levels of reliability. Those same environments can affect reliability strongly. The approach used for reliability and packaging qualification is referred to as the knowledge-based reliability approach. This section covers this concept in more detail.

Presentations

Use Conditions

This section covers the changes that are occurring in reliability for packaging. The industry is moving away from a “one size fits all” set of requirements to a use condition-based methodology, or one that takes into account the use conditions of the devices.

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Low-K Issues

This material covers low dielectric constant materials issues associated with the packaging process. Low-K materials are soft and have poor mechanical properties. This requires special approaches so that the packaging process does not damage these materials. Low-K materials also require special test techniques to monitor the affect of the packaging process on them.

Presentations

Low-K Issues

This section describes the problems related to packaging an IC that uses low-k dielectrics. It also describes several characterization methods for determining if a low-k dielectric will withstand the packaging process and the environment associated with its use conditions.

Copper Low-k Impact on Package Reliability

This section discusses a number of reliability failure mechanisms associated with interactions between the packaging process and the copper and low dielectric constant materials. It covers oxidation, corrosion, thermal cycling, wire pull and wire shear tests, and package stress.

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Polymers

Polymers are increasingly important materials used in today's semiconductor packages. Polymers are used in the mold compounds, underfill materials, redistribution layer and bump dielectrics, and substrate materials. In this course we cover the fundamental properties of polymers, the uses for polymers in microelectronics, and some examples from real-world situations.

Presentations

Mechanical Behavior of Solids

This section covers the mechanical behavior of polymers. This includes properties like glass transition temperature, the coefficient of thermal expansion, fracture toughness, elastic modulus, viscoelastic behavior, adhesion, peel strength, and water absorption.

Polymers - Introduction

This section provides an introduction to polymers used in packaging applications. The two major groups are polyimides and liquid crystalline polymers. It explains their chemical structure and their uses in electronic packaging.

Polymers - Basic Properties

This section explains the basic materials properties of polymers used in packaging applications. This includes polyimides and liquid crystalline polymers. We cover materials strength, temperature effects, moisture effects, anisothropy and glass transition.

Polymer Case Studies

This section covers three case studies involving problems with polymers in electronics applications. They include a coefficient of thermal expansion problem with a connector between a board and a daughtercard, degradation of a thermal interface material that holds a cooling pipe network in a package, and a delamination problem associated with water uptake in a polymer.

Specialty Polymers in Electronics

This section covers polymers that are used in semiconductor packaging applications. They include polyimides and liquid crystalline polymers. The chemical composition, shape, and properties are discussed.

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Die Connection Technologies

Die connection is an important consideration for today's IC and semiconductor packages. Wire bonding and wafer bumping are the two major technologies for making connections between the die and the package leadframe or substrate. We discuss the materials and technologies used to join the die to the package in this section. We discuss topics like copper wire bonding, copper pillar bumping, through silicon vias, and more.

Presentations

Cu Pillar Technology

This section provides an overview of copper pillar technology. It describes their use as a replacement to standard and lead-free solder balls, and discusses the advantages and disadvantages of this approach to die-to-substrate bumping.

Wire Bonding

Lead Finish and Trim, Solder Ball Attach

Bump Processes

Substrates

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Videos

Bond Shear Video

Wire Pull Test

Traditional Processes

This course discusses traditional processes used for packaging integrated circuits. This includes topics like: Wafer Saw, Leadframes, Die Attach, Wirebonding, Transfer Molding, Singulation, and Tape and Reel.

Presentations

Die Attach

This section covers information on die attach materials and dispense techniques. We primarily cover silver epoxies, and discuss their storage, use and issues associated with pattern dispense. We also discuss curing processes and issues associated with adhesion.

Leadframes

This section covers information on how one manufactures a leadframe for traditional leadframe products like Dual Inline Packages (DIPS), Quad Flat Packs (QFPs), and the like. We cover the leadframe materials, the two main processes of stamp and etch, the plating options, and the impact of surface roughness on bonding.

Dicing

Singulation

Packing and Shipping

Substrates

Underfills

Documents

Die Attach - Introduction

Die Attach - Temperature Issues

Videos

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Packaging Overview Video

Photovoltaics

Introduction

Photovoltaics, or solar cell technology, is a rapidly growing segment within the world economy. Many companies and organizations are pursuing a variety of solar cell technologies to create cost-effective, efficient electricity from the sun. Solar cell technologies fall into two main groups (thin film and bulk technologies). Within each group, engineers and scientists are pursuing both silicon and compound semiconductor materials. Some groups are even pursuing organic materials. Currently, our website covers silicon photovoltaics materials. We are also developing additional content that will cover compound semiconductor photovoltaic materials. The material covers both the technology and manufacturing of photovoltaics. It helps to illustrate the tradeoffs between cost and performance for this alternative energy source.

Presentations

Outline

This brief section provides an overview of the topics covered in the following presentations.

Introduction to Silicon Photovoltaics Technology

This section introduces photovoltaics as an energy source and explains why there is growing interest in the technology. It also discusses greenhouse gases and how solar energy can reduce the growth of greenhouse gases.

Properties of Sunlight

This section covers the properties of sunlight including the relationship between wavelength and energy, direct and diffuse sunlight, the standardized solar spectra, solar irradiance as a function of wavelength taking into account atmospheric effects, and insolation around the world.

Semiconductor Properties

This section covers the semiconductor properties that specifically pertain to solar cells. This includes crystal structure, doping, generation, light absorption in silicon as a function of temperature, wavelength and thickness. It also covers recombination, diffusion and drift as well as the basic p-n junction and pn diode equation.

Solar Cell Structure

This section describes the solar cell structure in terms of optimizing electron-hole pair generation and collection. It covers diffusion length effects, surface passivation and recombination, quantum efficiency, IQE, the photovoltaic effect and the current-voltage characteristics. It also discusses the effects of loading and series resistances and dark current light intensity effects, and temperature effects.

Design of Silicon Cells

This section covers the basic design principles involved in creating an efficient silicon photovoltaic cell. It covers anti-reflection coatings, surface texturing, recombination, back surface fields, resistance effects in the silicon, contacts, as well as the interconnect. There is also a discussion of compromises that need to be considered when designing a cell panel.

Manufacturing Cells

This section covers the manufacturing steps involved in creating a silicon solar cell. It covers silicon crystal growth, wafer or panel slicing, diffusion of dopants, the screen printing process, buried contact technology, and configurations such as PERL and emitter wrap-through cells.

Solar Cell Production Line

This section describes the factory process steps associated with the manufacture of the silicon photovoltaic cells. It includes the growth process, wafer sawing systems, texturing, the diffusion and isolation processes, the anti-reflection coating process, the screen printing process, the firing process, and final test and sort.

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Processes

Introduction

Fabrication of semiconductors and integrated circuits (ICs) is arguably one of the most advanced manufacturing processes ever developed. A state-of-the-art IC requires a ultra clean environment, ultra pure chemicals and gases, highly sophisticated fabrication tools, and a team with extensive knowledge of chemical engineering, semiconductor physics, modeling, and logistics management. The materials in this section cover the main disciplines or steps used in semiconductor fabrication. They include:

  • Growth and preparation of the starting material (Si, GaAs, or other semiconductor materials)
  • Diffusion
  • Oxidation
  • Cleaning
  • Ion Implantation
  • Lithography
  • Chemical Vapor Deposition
  • Physical Vapor Deposition
  • Chemical Mechanical Planarization

Please click on the topics to the left to begin learning about this fascinating process.

Crystal Growth

Semiconductor devices and integrated circuits require extremely pure silicon for processing. Refining silicon and creating the wafers is a complex process in and of itself. This course covers the purification methods, the crystal growth process, wafer sawing, polishing and identification, and the epitaxial growth process. We also cover the range of silicon defects, discussing their origins and how to eliminate or mitigate these problems and their effects.

Presentations

Starting Material - Bulk Silicon Process

This section covers the basics of silicon crystal structure, defects, the growth process, sawing, and wafer identification.

Wafer Specifications and Defects

Silicon on Insulator Process

Epitaxial Growth Process

Quiz: Crystallinity, Crystal Defects and Crystal Growth

Documents

Starting Material

Several topics dealing with starting material (silicon) are discussed in this chapter. Some of them include the manufacture of single crystal silicon, incorporation of impurities, float zone process, wafer sawing and wafer dicing operations, silicon on insulator, and silicon crystal defects.

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Ion Implantation

Ion implantation is the most accurate and controlled method for placing dopant atoms within the source, drain, threshold adjust regions, and guardbands. Ion implanters acclerate dopant species to high velocities and force them into the silicon lattice to form the transistors, junctions, and other structures in the integrated circuit. In this course we cover the fundamentals of ion implantation, the applications of the technique, the basic equipment configurations, including high voltage and high current systems, and issues associated with the technique.

Presentations

Ion Implantation Process Issues

This section goes into detail on some of the more common problems and issues associated with Ion Implantation. It covers challenges like charge neutralization, energy contamination, wafer charging, wafer heating, photoresist outgassing, implant angle effects, and ultrashallow junction formation.

Ion Implantation - Equipment

Quiz: Ion Implantation

Documents

Ion Implantation Part I - Equipment

Ion Implantation - Process Issues Part I

Ion Implantation - Process Issues Part II

Videos

Ion Implantation Animation

Thermal Processing

Thermal Processing is an important class of techniques for semiconductor manufacturing. This includes classical thermal techniques like diffusion and oxidation, along with newer techniques that fall into the category of Rapid Thermal Processing (RTP). In this class we cover diffusion (using temperature to drive dopant atoms into the semiconductor) and oxidation (using temperature to grow an oxide - either slowly in a dry environment or quickly in a steam environment). These techniques can be used early in the manufacturing sequence, but cannot be used in the back end of the line due to the high temperatures. They also do not work well with advanced processes. We also cover RTP, where engineers use systems that elevate the temperature for very short periods of time to provide better control.

Presentations

Thermal Processing Overview

This section is an overview of thermal processing. This includes thermal oxidation, thermal annealing, thermal diffusion and thermal nitridation. This section also discusses the process applications associated with silicon dioxide.

Thermal Processing Oxidation and Kinetics

This section discusses the basic properties of silicon dioxide. It describes how an thermal oxide is formed and the reaction kinetics. It also discusses the Deal-Grove model in more detail as it applies to thermal oxidation.

Thermal Processing Equipment and Processing

This section covers both equipment and processing steps for thermal processes. It includes information on oxidation furnaces and rapid thermal processing hardware. It also describes monitoring and metrology techniques for oxide thickness, variation, and film quality. Finally, it describes the basic oxidation sequence for thermal silicon dioxide.

Thermal Processing Issues and Effects

This section covers issues and effects associated with thermal processing. We discuss the Deal-Grove model as it applies to thermal processing, and discusses effects caused by doping, crystal orientation, pressure, and post treatments. This section also includes information of oxide charges and their effect on MOS electrical behavior.

Oxidation

This section covers wet and dry oxidation. We cover oxidation models as well as concentration effects.

Diffusion

This section covers the diffusion process. We discuss the physics of diffusion, dopant species, electrical, and concentration effects.

Thermal Diffusion

Rapid Thermal Processing

Quiz: Thermal Processing

Documents

Thermal Processes and Oxide Material Basics

Thermal Processing Equipment

Thermal Processing Parameters and Dependencies

Videos

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Contamination and Cleaning

Cleaning is an important part of most processing steps. We need techniques to remove particulates, liquids, and contamination from the surface of the wafer. This class discusses the techniques that perform these cleaning operations. This includes liquid chemical techniques like the piranha etch, dry cleaning, and aerosol cleaning. We also discuss rinsing and drying techniques in the section.

Presentations

Wafer Cleaning Overview and Procedures

This section discusses the challenges associated with wafer cleaning. We cover techniques for particle removal which includes both chemical and mechanical removal. We also cover electrochemistry and various cleans like the RCA clean, supercritical carbon dioxide cleans and UV/ozone cleans.

Wafer Cleaning Methods and Equipment

This section covers the methods and equipment used to clean wafers after various processing steps. This includes methodologies like spray, immersion, and centrifuge. We also include information on tools that perform chemical cleans, scrubbing, mechanical cleans, cryogenic cleans, and injected energy cleans like ultrasonic and megasonic cleans.

Contamination Control

Quiz: Contamination Monitoring and Wafer Cleaning

Documents

Cleaning Methods

Videos

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Vacuum and Plasma Basics

Vacuum Technology is an integral part of the semiconductor industry. Many tools use vacuum chambers and vacuum technology to control the placement of ions, manipulate reactions and depositions, and minimize contamination. This course covers the basics of vacuum systems and the technologies used to create a vacuum. We also discuss plasma basics, since plasma physics is closely tied to vacuum technology, and since we use plasma physics in various semiconductor processing steps like chemical vapor deposition and reactive ion etching.

Presentations

Vacuum Concepts

This section covers basic vacuum concepts. We begin with a treatment of the theory of gases from a non-mathematical perspective. We then discuss vacuum basics, including definitions, gas-solid gas-liquid interactions and gas flow regions. We then end with an overview of pump types used in the semiconductor industry.

Vacuum Systems

This section covers vacuum systems in more detail. It includes details on pumps such as cryopumps, turbomolecular pumps, momentum transfer pumps and displacement pumps. It also includes information on other vacuum system components like mass flow controllers, leak detection, residual gas analysis, pressure gauges, and gas treatment systems.

Plasma Basics

This section covers the basics of plasma technology. It describes how a plasma is formed and the common homogenous reactions. It also describes how the space charge region works in the chamber.

Quiz: Vacuum, Thin Film and Plasma Basics

Documents

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Videos

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Physical Vapor Deposition

Physical Vapor Deposition (PVD) is a common method for depositing thin-film metals on a semiconductor device. There are primarily two types of PVD: evaporation and sputtering. This course covers both techniques and describes the advantages and disadvantages of each. It covers the basic properties of thin films and the impact of the vacuum chamber on their quality. It also discusses variations on sputtering, including ionized and collimated sputtering.

Presentations

Deposition

This section covers physical vapor deposition and chemical vapor deposition techniques.

Evaporation

This section covers evaporation as a deposition technique for semiconductor processing. It discusses the two main techniques for evaporation, process issues associated with evaporation, the problems with the technique, and why it is not generally used in the semiconductor industry today.

Thin Film Basics

This section covers the basic ideas for thin film layers. It discusses how one grows or deposits thin films, along with basic models for their growth. The section also discusses important thin film properties like thickness, resistivity, grain size, roughness, density, stress, and more.

Sputtering

This section provides an introduction to sputtering processes. It includes information on the basic physical process of sputtering. It describes the sputter deposition process, along with the equipment used for these materials. It also includes process information on how to improve step coverage and contact or via hole filling.

Sputtered Films

This section discusses the sputtering process. It primarily discusses sputtering of aluminum and aluminum alloys. It includes information on junction spiking, electromigration, step coverage, and topics like collimated sputtering and ionized PVD. It also includes information on the equipment used for thin film thickness and characterization.

Quiz: Physical Vapor Deposition

Documents

Deposition

The deposition topics covered here include silicon epitaxial growth, physical vapor deposition, sputtering, molecular beam epitaxy, chemical vapor deposition (CVD), spin-on dielectrics, and electroplating.

Videos

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Chemical Vapor Deposition

Chemical Vapor Deposition (CVD) is a highly versatile process used by the semiconductor industry to deposit materials. CVD allows the deposition of a wider range of materials, and can be used at lower temperatures (under certain conditions) than other deposition techniques. In this course we will cover the main approaches to CVD: Plasma Enhanced CVD (PECVD), Low Pressure CVD (LPCVD), and Atmospheric Pressure CVD (APCVD). We will also cover the applications of CVD, including deposition of dielectric layers like silicon dioxide and silicon nitride, polysilicon, metals like tungsten, and other liner materials like titanium nitride. We will cover the equipment used for CVD, and the issues associated with the technique.

Presentations

Deposition

This section covers physical vapor deposition and chemical vapor deposition techniques.

CVD - Basics

This section provides an introduction to Chemical Vapor Deposition (CVD). It describes the generic CVD process, discusses the Deal-Grove model, and outlines the 4 CVD processes, including traditional CVD, Atmospheric Pressure CVD, Plasma Enhanced CVD, and Low Pressure CVD.

CVD - Applications

This presentation discusses the major applications for Chemical Vapor Deposition (CVD). We discuss CVD for dielectric deposition, which includes gate and interlevel dielectrics, metals deposition, which includes aluminum, titanium, and tungsten, and other materials like polysilicon.

CVD - Epitaxy

Low Pressure CVD

This presentation discusses Low Pressure Chemical Vapor Deposition (LPCVD). We contrast LPCVD to Atmospheric Pressure CVD (APCVD), and discuss the advantages and disadvantages of the process. We also discuss the use of LPCVD for tasks like silicon nitride and polysilicon deposition. We also describe the LPCVD reactor and how it works.

Plasma Enhanced CVD

Quiz: CVD Basics, LPCVD and Epitaxy

Documents

Deposition

The deposition topics covered here include silicon epitaxial growth, physical vapor deposition, sputtering, molecular beam epitaxy, chemical vapor deposition (CVD), spin-on dielectrics, and electroplating.

CVD - Basics

CVD - Applications

CVD - Epitaxy

Videos

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Lithography

Lithography is a key component of IC manufacturing. It is also one of the most expensive steps in the IC manufacturing process. Today's ICs go through the lithography step some 20 to 30 times to pattern the isolation layers, transistors, gates, and interconnect. Lithography is also used in the packaging process as well. This material covers the physics of lithography, resolution, the photoresists used in lithography, and lithography techniques.

Presentations

Lithography - Introduction

This section provides an overview of lithography. It describes basic concepts such as optics, resist, and printing.

Lithography - Resolution

This section discusses resolution as it applies to lithography. It covers properties of light, diffraction, phase shift masking, and optical proximity correction.

Lithography - Resists

This section covers both positive and negative resists for lithography. It also covers hard mask technology.

Lithography - Subwavelength Issues

This section provides a quick review of wavelength, numerical aperture, and k-factors, and their relationship to lithography. The material provides an overview of immersion lithography. This section also covers techniques currently used while waiting for the transition to Extreme Ultraviolet Lithography (EUVL) like source optimization, mask engineering techniques like subwavelength resolution assist features, and double patterning approaches. It concludes with an overview of EUVL, discussing its advantages and disadvantages.

Lithography - Future

This section covers the future of lithography. It includes discussions on EUVL, SCALPEL, X-ray lithography, nano-imprint lithography, and immersion lithography.

Quiz 10: Lithography Photoresist Processing

Quiz: Lithography Image Formation and Photomasks

Documents

Lithography

Videos

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Etch

Etch is widely used for removing thin films on semiconductor devices. The industry primarily uses reactive ion etching for layer removal, although wet chemical etching is occasionally used in some processes. This course covers the fundamentals of plasma physics, as well as the application of plasma and reactive ion etching to semiconductor fabrication.

Presentations

Dry Etching Processes

This section covers reactive ion etch processes for removing materials from a semiconductor device.

Wet Etching Processes

This section covers wet etch processes for removing materials from a semiconductor device.

Plasma Basics

This section covers the basics of plasma technology. It describes how a plasma is formed and the common homogenous reactions. It also describes how the space charge region works in the chamber.

Plasma Etching and RIE

This section describes the fundamental differences between plasma and reactive ion etching. It describes the basic configurations, the etch gases and parameters that affect the etch rates. It also includes information on topics like sidewall passivation, aspect ratio dependent etching, and other issues.

Quiz: Wet Etching and Reactive Ion Etching

Documents

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Videos

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Chemical Mechanical Polishing

Chemical Mechanical Polishing (CMP) is probably the single most important breakthrough that allowed the semiconductor industry to deposit more than 2 levels of metal reliability and permit the continued scaling of integrated circuit feature sizes. CMP uses a combination of chemicals and mechanical force to planarize the metal and dielectric layers on an integrated circuit. In this course we cover the basic techniques for CMP, the equipment used for CMP, and the applications of the technique.

Presentations

Chemical Mechanical Polishing - Overview

CMP - Equipment

CMP - Applications and Issues

Quiz: Chemical Mechanical Polishing

Documents

Chemical Mechanical Polishing

Various aspects of CMP are discussed, including CMP variables and physics, Oxide CMP, Tungsten CMP, Copper CMP.

CMP - Applications and Issues - Part I

CMP - Applications and Issues - Part II

Videos

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Copper and Low-K Dielectrics

In order to achieve higher performance in today's integrated circuits, engineers have replaced aluminum and silicon dioxide with newer materials. Many high performance chips use copper interconnect and low-k dielectrics to reduce the RC delay associated with the interconnect. Copper has a lower resistance than aluminum, and has superior electromigration performance. Scientists have developed low-k dielectrics with various materials, like fluorinated glasses, carbon-doped oxides, and nanopore materials with significantly lower dielectric constants. While there are advantages to these materials, there are also issues, like copper contamination in transistors, patterning of copper materials, and structural integrity and strength of low-k dielectrics. We discuss these issues in this course.

Presentations

Low-K Dielectrics

Copper Interconnect

Documents

Copper Interconnect

Videos

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Special Processing Techniques

Scientists and engineers in the semiconductor industry have developed a number of special techniques to address specialized markets and advanced applications. This course covers some of those techniques. This includes atomic layer deposition, which is used increasingly for high-k gate dielectrics and liner materials, bonding and implant techniques for silicon on insulator (SOI) substrates, which are used for low power and radiation environments, new rapid thermal annealing techniques, and advanced ion implantation methods.

Presentations

Special Processing Techniques

This section describes several process integration techniques that are important for an understanding of today's integrated circuits. It includes topics such as Silicon on Insulator, Atomic Layer Deposition, Rapid Thermal Annealing, and Implant Techniques. These are also discussed in other sections as well.

Documents

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Videos

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Process Integration

Fabrication of semiconductors and integrated circuits (ICs) is arguably one of the most advanced manufacturing processes ever developed. A state-of-the-art IC requires a ultra clean environment, ultra pure chemicals and gases, highly sophisticated fabrication tools, and a team with extensive knowledge of chemical engineering, semiconductor physics, modeling, and logistics management. The materials in this section cover the main disciplines or steps used in semiconductor fabrication. They include:

  • Growth and preparation of the starting material (Si, GaAs, or other semiconductor materials)
  • Diffusion
  • Oxidation
  • Cleaning
  • Ion Implantation
  • Lithography
  • Chemical Vapor Deposition
  • Physical Vapor Deposition
  • Chemical Mechanical Planarization

Please click on the topics to the left to begin learning about this fascinating process.

Presentations

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Documents

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Videos

Basic CMOS Process Animation

This animation describes the major processing steps performed when fabricating a basic CMOS integrated circuit. The transistors and interconnect are viewed from a cross-section perspective during the fabrication process.

Basic CMOS Manufacturing Process in 3D

22nm FinFET Technology

45nm Hi-K Metal Gate Technology

180nm CMP Technology with Tungsten Vias

250nm High-Voltage BiCMOS Technology

350nm LOCOS Field Isolation CMOS Technology

350nm STI Field Isolation CMOS Technology

Materials for Processing

This course covers the materials that are used in semiconductor processing. The main focus of this material is on low-k materials, but will be expanded to include chemicals and gases.

Presentations

Alternate Channel Materials

This section covers new semiconductor materials that are candidates to replace silicon in the channel of state-of-the-art and future transistors. We cover GaAs, InGaAs, Ge, and others. We also discuss issues related to mobility, stress and strain, and bandgap.

Alternate Gates

Low-K Materials

This section describes a number of low-k materials that are being considered for semiconductor manufacturing.

Copper Interconnect

Etch Stop Materials for Low-K Applications

This section discusses etch stop materials and hard masks that are used in conjunction with low dielectric constant materials in semiconductor processing.

Documents

Copper Interconnect

Videos

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Bipolar and BiCMOS

Designers use Bipolar and BiCMOS technologies when they must accurately control and manipulate analog signals. The bipolar transistor has several qualities that allow the engineers to better control the behavior of the circuit, like better matching, lower noise levels, higher current drives, and higher cutoff frequencies. We discuss the physics of bipolar circuit operation, basic bipolar processes, and BiCMOS processes.

Presentations

Silicon Properties

This section provides an introduction to silicon properties that are important to semiconductor fabrication. It includes material on Fermi Level and energy band diagrams. The material discusses the Fermi potential, drift, current density, conductivity and resistivity of silicon, carrier transport, mobility and scattering mechanisms as well as Matthiessen's rule. The section also covers transitions due to energy states within the silicon due to doping and impurities and ends with a discussion on minority carrier diffusion length.

Conventional BiCMOS

This section introduces BiCMOS processing, or the combination of bipolar and MOS transistors on a single chip. It describes the advantages of BiCMOS, applications in which it is used, and the disadvantages. It covers the basic BiCMOS process through several cross-section examples, and goes into high-level descriptions of the major processing modules associated with a standard BiCMOS process.

Bipolar Enhancement Techniques

This section covers techniques to improve the performance of bipolar transistors. It focuses mainly on polysilicon emitters for better junction control, silicon-germanium (SiGe) material substitution in the base region to improve mobility and transit times, and silicon-germanium-carbon (SiGe:C) to control transient enhanced diffusion effects.

Contacts

This section covers the basic device physics for metal to silicon contacts. It includes details on rectifying contacts, ohmic contacts, and the Schottky barrier diode.

Documents

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Videos

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CMOS

CMOS (Complementary Metal Oxide Semiconductor) is the most common chip technology in use today. More than 90% of all integrated circuit fabricated today use CMOS technology. CMOS makes excellent digital logic because of its large digital noise immunity and low background current. This course covers the properties of silicon, the behavior of the MOS capacitor, the p-n junction, and the device physics of the MOS transistor.

Presentations

Silicon Properties

This section provides an introduction to silicon properties that are important to semiconductor fabrication. It includes material on Fermi Level and energy band diagrams. The material discusses the Fermi potential, drift, current density, conductivity and resistivity of silicon, carrier transport, mobility and scattering mechanisms as well as Matthiessen's rule. The section also covers transitions due to energy states within the silicon due to doping and impurities and ends with a discussion on minority carrier diffusion length.

LOCOS and STI

This section provides an overview of the basic process integration steps associated with transistor isolation. Specifically, we discuss LOCal Oxidation of Silicon (LOCOS) and Shallow Trench Isolation (STI).

Gate First vs. Gate Last

This brief section describes how process engineers handle the high-k/metal gate CMOS transistor. It describes the terms gate first, gate last, and replacement gate.

Special Processing Techniques

This section describes several process integration techniques that are important for an understanding of today's integrated circuits. It includes topics such as Silicon on Insulator, Atomic Layer Deposition, Rapid Thermal Annealing, and Implant Techniques. These are also discussed in other sections as well.

Mobility Enhancement Techniques

This section provides information on mobility enhancement techniques, or techniques to improve the operation of transistors. We discuss strained silicon and the enhancements that can be made to a transistor using strain. We also discuss using silicon-germanium (SiGe), stress liners, and other techniques. This section then discusses alternate orientation, or hybrid orientation techniques (HOT), using 110 orientation PMOS and 100 orientation NMOS. Finally, we discuss the use of alternate channel materials like germanium and gallium arsenide (GaAs).

Source Drain Extensions

This section covers techniques for improving source/drain performance. It includes information on raise source/drain regions, angled implants (also known as halo or pocket implants), carbon implantation, co-implantation of inactive species, pulsed plasma doping, and Schottky Barrier source/drain MOSFETs.

Contacts

This section covers the basic device physics for metal to silicon contacts. It includes details on rectifying contacts, ohmic contacts, and the Schottky barrier diode.

Salicide and BEOL

This section provides an overview of the salicide process and the contact formation process.

Quiz: Basic CMOS Process Flow

Process Integration Quiz

This quiz tests the student's general knowledge of CMOS and BiCMOS Process Integration. The quiz includes questions on device physics, basic processing, materials, reliability and yield.

3D Structures

CMOS Design Considerations

Documents

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Videos

Cross Section

Product Qualification

Product Qualification is the group of activities that semiconductor manufacturers perform to demonstrate to their customers that their devices will be fit for the use to which they were designed. These activities are primarily testing activities, designed to demonstrate that the device will meet its physical dimensions, electrical characteristics, and reliability projections. We discuss these activities, and the standards by which we perform Product Qualification, in this classroom.

Qualification Standards

Qualification is an important activity for product and reliability engineers. In order for the industry to be comfortable using a component, they decided to create several standards, allowing semiconductor manufacturers and users to "agree" on what constitutes a qualified product. We discuss those standards in this course.

Presentations

Product Qualification Overview

MIL-STD Qualification

Failure Mechanism Driven Qualification

Stress Driven Qualification

AEC Q100 Qualification

Knowledge Based Qualification

Documents

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Videos

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Reliability Testing

Testing is a key aspect of reliability evaluations. Testing must be performed not only for individual failure mechanisms, but also at the component level. Component level testing helps ensure that all potential failure mechanisms are addressed. There are two types of testing at the component level: electrical screens and stress/life tests. Electrical screens are performed using automated test systems and are similar to standard functional tests. Stress and life tests are performed over longer periods of time under accelerated conditions. These conditions could be higher voltage levels, higher temperatures, high humidity levels, or a combination of each.

In order to make an accurate prediction concerning the reliability of a component or system, one must have data on the behavior of the system, or its individual components or failure mechanisms. While these can be estimated based on other experiments or data, it is best to gather data from the system, components, or surrogate test structures directly. This material describes test structures, test equipment, and the type of tests that are performed to generate reliability data. It includes material on burn-in, humidity testing, thermal cycling, and other types of accelerated testing.

Presentations

Developing Electrical Screens

This section covers electrical and parametric screens that are performed to aid in the reliability evaluation of an IC.

Developing Stress Tests and Life Tests

This section covers burn-in, life tests, HAST testing, and other humidity testing used to evaluate the reliability of packaged ICs.

Documents

Screens, Stress Tests and Life Tests

Overview of screens and various tests. Topics include: ATE based screens, IDDQ, statistical process control, burn-in, life tests, highly accelerated stress test, acceleration factors and distributions, equipment, times, temperature, and biasing.

Videos

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Reliability Overview

Introduction

Reliability is defined as the intrinsic "goodness" of a component, and implies that a component will work according to its specification for some defined period of time. In order to understand reliability, one must have a basic understanding of the following items:

  • Reliability Terms and Definitions
  • Statistics and Distributions
  • Failure Mechanisms (die level, package level, system level, and use conditions)
  • Test equipment
  • Test structures
  • Accelerated testing techniques

This material covers these six topics in detail, including reliability terms, statistics and distributions, calculating reliability, test equipment and structures, and the methods for determining the operational (and non-operational) lifetime of a microsystem. It also covers the physics and the methods used for determining the various mechanisms that can cause performance degradation.

Introduction to Reliability

Reliability is an important aspect of semiconductor design and manufacturing. Customers expect devices to work correctly through the expected life of the component. In some applications like medical implants, defense, and space, the consequence of failure is enormous. This requires extra attention to reliability. This material introduces the subject of reliability to the engineer/scientist.

Presentations

Introduction to Semiconductor Reliability

This section provides a history of reliability activities, introduces basic terminology, and discusses the link between reliability and yield.

Documents

Quality for Reliability Overview

This document provides an overview of the Design for Reliability Process. It describes steps that can be taken at the Transistor Level, Gate or Libraries Level, Microarchitecture Level, and Core or Chip Level, to improve the reliability of the component. This includes improving reliability through operation adjustment, and ensuring that one can take advantage of the entire life of the chip through more detailed assumptions and modeling rather than assuming worst-case conditions.

Quality and Reliability

Here we talk in general about quality (process variation and control), reliability, failure mechanisms (ESD, stress voiding, etc), and yield.

Videos

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Design for Reliability

Design for Reliability is increasingly a part of the design engineer's activities. Design for Reliability is the process of ensuring that major failure mechanisms will have minimal impact on the overall operation of the integrated circuit. Design for Reliability occurs at all levels of the process, from the transistors all the way up to the core or chip level. These presentations provide an overview of the Design for Reliability process.

Presentations

Design for Reliability - Introduction

This section provides an introduction to the topic of design for reliability. It covers the reason why design for reliability is becoming an increasingly important topic and describes the design stages at which design for reliability is performed: transistor level, cell library level, microarchitecture level, and core/chip level.

Design for Reliability - Transistor Level

This section describes compact, subcircuit, and SPICE models that can be used to simulate process variability and reliability degradation. This can be done for local variations or global variations.

Design for Reliability - Library Level

This section contains information on how Design for Reliability is performed at the Gate or Library cell level. It includes information on modeling variability within digital cells, analog cells, and memory elements. It discusses the effect of TDDB, Hot Carriers and NBTI on timing and read/write characteristics.

Design for Reliability - Micro Architecture Level

This section contains design strategies for reliability at the microarchitecture level. This includes techniques to allow for different sizing of gates, techniques for analyzing signal probabilities associated with degradation, controlling inputs to minimize degradation, and synthesis activities.

Design for Reliability - Core Chip Level

This section describes the Design for Reliability activities that occur at the Core/Chip Level. It contains information on topics like Adaptive Body Bias and Adaptive VDD.

Documents

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Videos

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Reliability Statistics

Introduction

One important aspect of reliability engineering is statistics. The reliability engineer should have a good grasp of statistics and distributions. All reliability-related failure mechanisms can be mapped to a particular distribution type. The most common distributions used in reliability studies are the exponential distribution, the normal distribution, the lognormal distribution, and the Weibull distribution.

Reliability is a discipline driven by data. In order to predict the reliability of a component, one must use test data to predict the response of the component or electronic system. This requires an in-depth understanding of statistics and distributions. This material covers basic statistics and distributions used for reliability calculations, how to handle situations where no failures occur, how to transform data from test structures to use conditions, and how to calculate system level reliability based on individual reliability numbers from components or failure mechanisms.

Presentations

Acceleration and Number of Failures

Plotting Data

Reliability Distribution Types

Basic Reliability Statistics

Statistics and Distributions Quiz

This quiz covers statistics and distributions as it relates to semiconductor reliability

Which Distribution Should I Use?

This section covers the issues associated with choosing a distribution to fit a given set of data.

Distribution Graphing Problems

This set of problems covers graphing exponential, normal, lognormal, and Weibull distributions.

Lognormal Distribution Example

This file provides an example of a lognormal distribution and how to plot a lognormal distribution in Excel

Probability of Lot Acceptance

This file allows the user to plot the probability of accepting a specified sample given a lot PPM figure.

Calculating Component/System Level Reliability

This section describes the common methods used for calculating an overall component reliability or system reliability from individual reliability data. This includes bottoms-up approaches and top-down approaches.

Outlier Screening

Documents

Reliability Graphing Paper

This file contains Lognormal, Weibull, and Semi-Log (Exponential) graphing paper.

Standard Normal CDF Table

This table contains calculated Standard Normal CDF values. These are used for calculating system reliability numbers when lognormal distributions are involved.

Videos

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Reliability Testing

Introduction

Testing is a key aspect of reliability evaluations. Testing must be performed not only for individual failure mechanisms, but also at the component level. Component level testing helps ensure that all potential failure mechanisms are addressed. There are two types of testing at the component level: electrical screens and stress/life tests. Electrical screens are performed using automated test systems and are similar to standard functional tests. Stress and life tests are performed over longer periods of time under accelerated conditions. These conditions could be higher voltage levels, higher temperatures, high humidity levels, or a combination of each.

In order to make an accurate prediction concerning the reliability of a component or system, one must have data on the behavior of the system, or its individual components or failure mechanisms. While these can be estimated based on other experiments or data, it is best to gather data from the system, components, or surrogate test structures directly. This material describes test structures, test equipment, and the type of tests that are performed to generate reliability data. It includes material on burn-in, humidity testing, thermal cycling, and other types of accelerated testing.

Presentations

Developing Electrical Screens

This section covers electrical and parametric screens that are performed to aid in the reliability evaluation of an IC.

Developing Stress Tests and Life Tests

This section covers burn-in, life tests, HAST testing, and other humidity testing used to evaluate the reliability of packaged ICs.

Documents

Screens, Stress Tests, and Life Tests

Overview of screens and various tests. Topics include: ATE based screens, IDDQ, statistical process control, burn-in, life tests, highly accelerated stress test, acceleration factors and distributions, equipment, times, temperature, and biasing.

Videos

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Reliability Test Equipment

Reliability test equipment is an important consideration for accelerated testing. Reliability testing is performed at the wafer level and at the packaging level. In order to provide more timely feedback, manufacturers prefer to use wafer level testing. This section discusses equipment for both wafer level and packaged part level. We also cover probe technology for wafer level probing.

Presentations

Reliability Test Equipment - Wafer Level

This section covers wafer level reliability test equipment. It includes material on probers, source measurement units, switch matrices, and software.

Reliability Test Equipment - Probes

This section covers probe card and probe tip technology for wafer level probing.

Reliability Test Equipment - Packaged Parts

This section covers reliability test equipment that is designed for testing packaged ICs. It includes discussions on burn-in equipment, humidity testing, and other reliability-related testing.

Documents

Test Equipment

This short chapter talks about wafer-level reliability equipment and package-level test systems.

Videos

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Reliability Test Structures

Testing at the wafer level requires appropriate electrical elements on the wafer. These electrical structures must simulate and magnify problems that normally occur on finished components. This section discusses test structures and their use in reliability testing.

Presentations

Test Structures - Basics

This section covers basic test structures and their use for reliability characterization. It also includes basic information on the purpose of test structures.

Reliability Test Structures

This section covers test structures that are designed specifically for reliability characterization. This section describes TDDB-specific structures and how they can be designed to help separate and identify different effects.

Self Stressing Test Structures

This section covers self-stressing test structures and their use in more accurately characterizing reliability degradation mechanisms.

Documents

Test Structures

This chapter discusses parametric test structures, reliability test structures, and self-stressing test structures.

Videos

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Technology

Introduction

Semiconductor Technology encompasses the fundamental device groups and the methods used to create these technologies. This encompasses Logic Devices (Digital), Analog Devices, Mixed Signal Devices (Analog and Digital on the same chip), Memory Devices, High Voltage Devices, High Frequency Devices, Optoelectronics, and Micro Electro Mechanical Systems (MEMS). There are a number of key processes that enable these devices that include CMOS (Complimentary Metal Oxide Semiconductor), Bipolar, MESFET (Metal Electrode Semiconductor Field Effect Transistors, and a wide range of lesser processes.

Presentations

Basic CMOS Process Animation

This animation describes the major processing steps performed when fabricating a basic CMOS integrated circuit. The transistors and interconnect are viewed from a cross-section perspective during the fabrication process.

Documents

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Videos

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Interconnect Technology

Today's ICs may contain kilometers of interconnect and billions of vias, so the interconnect system must be manufactured with the utmost precision. This course covers issues associated with interconnect on semiconductor devices. It covers both aluminum and copper interconnect systems.

Presentations

Interconnect Scaling Overview

This presentation provides a brief overview of the issues associated with scaling an integrated circuit and its effect on the interconnect.

Documents

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Videos

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Memory Technology

This material covers the technology of memory ICs. Memory is ubiquitous in today's electronic systems. There are several types of memory: dynamic random access memory (DRAM), static random access memory (SRAM), and non-volatile memory (NVM). Each has its advantages and disadvantages, and each has different design and manufacturing techniques.

Presentations

Memory Technology Overview

This section provides an overview of memory technology. It covers Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Non-Volatile Memories like NAND and NOR flash. It also covers a history of the basic non-volatile memory technologies, including NMOS, SONOS, FLOTOX, and flash memory.

DRAM Introduction and Scaling

This section describes the scaling issues associated with dynamic random access memory (DRAM). It goes into detail describing the DRAM tables within the International Technology Roadmap for Semiconductors (ITRS) and upcoming difficulties. The section then summarizes the major themes driving these difficulties which include: leakage, power dissipation, patterning, and new transistor architectures for the access transistor.

DRAM Technology

Atom Switch Technology

Fusible Link Technology

Quartz Disc Storage Systems

Documents

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Videos

Energy Band Transitions

This animation covers the basic energy band transitions that can occur, including: interband transitions, intraband transitions, and assisted transitions.

pn Junction Diodes

This interactive graph demonstrates the current voltage characteristics of a pn junction or diode. We plan to add more details to the operation of this graph in the near future.

SOI Technology

Silicon on Insulator Technology is an important technology for addressing difficult problems within the semiconductor industry. Silicon on Insulator, or SOI, is the process of building semiconductor devices on a thin insulating layer, or on a sapphire (aluminum oxide) substrate. The common technique today is to create a very thin insulating layer. SOI Technology is used for creating devices that are immune to CMOS latchup. It is also used to create low power circuits. These presentations describe SOI Technology in more detail.

Presentations

Silicon On Insulator Overview

This section covers Silicon on Insulator (SOI). It discusses the advantages and disadvantages of the technology, partially and fully depleted SOI, the techniques for creating SOI wafers, and the outlook for SOI's use as a substrate for CMOS technologies.

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Compound Semiconductor Technology

Compound Semiconductors are used increasingly in today's electronics. Cellular phones, power amplifiers, lasers, and even switching transistors for hybrid electric vehicles utilize compound semiconductor devices. In the near future, we are also likely to use compound semiconductor materials in CMOS transistors. This section provides presentations and material on Gallium Arsenide (GaAs), Gallium Nitride (GaN), and Silicon Carbide (SiC).

Presentations

Silicon Carbide Failure Mechanisms

This section provides an overview of the more common silicon carbide (SiC) failure mechanisms. It discusses techniques for silicon carbide growth and the defects associated with the growth process like micropipes and dislocations. It covers the major failure mechanisms: time dependent dielectric breakdown and single event upset.

Gallium Nitride Failure Mechanisms

This section provides an overview of the more common gallium nitride (GaN) failure mechanisms. It includes details on parasitic effects like current collapse, excess leakage current, the Kink effect, and hot electron degradation. It also includes details on degradation mechanisms like gate leakage current, trap buildup in the dielectric layers and the interfaces, gate metal diffusion, and ohmic metal degradation.

Gallium Arsenide Failure Mechanisms

This section provides an overview of the more common gallium arsenide (GaAs) failure mechanisms. It includes information on hydrogen sensitivity (or poisoning) in field effect transistors and heterojunction bipolar transistors, metal-insulator-metal (MIM) capacitor breakdown, metal and contact migration, dark line defects, recombination enhanced defect reaction, and trap formation in the base region of heterojunction bipolar transistors.

Compound Semiconductor Materials

This section provides an overview of the materials properties associated with compound semiconductors. We cover gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) in some detail, and mention other compound materials briefly. We discuss growth techniques and the physical properties of these materials. This includes thermal conductivity, mobility, bandgap structure, breakdown strength, and other properties.

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Power Device Technology

This material covers topics related to Power Transistors and Power Integrated Circuits. Power devices typically operate at voltages above 5 volts and current values in excess of 100mA. This is a growing area for device development, and there are numerous types of devices and technologies. These devices are common in power converters, inverters, chargers, regulators, and other high voltage circuits.

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Smart Power Devices - Fundamentals

Smart Power Devices - Issues

Smart Power Devices - Integration Options

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Test

Introduction

This workspace covers semiconductor and integrated circuit test. Test is a critical aspect of the design and manufacturing process. Test allows one to determine if the device is working correctly, and it can also give insight into potential failure mechanisms and manufacturing issues. In this section we cover: defect modeling, design for test, digital testing, analog testing, parametric testing, and test hardware.

Defect Based Testing

Defect-based testing is the practice of testing with the idea of detecting defective conditions on complex ICs. Defect-based testing moves beyond functional and structural testing by introducing test concepts to catch actual defects. Many defects are not easily caught with standard test techniques, and require additional test approaches. Defect-based testing incorporates knowledge of defects like opens, shorts, resistive connections, parametric anomalies, and process variation-induced problems. It requires an understanding of the electrical behavior of these defects. The electrical behavior can be turned into a defect model, which in turn leads to effective test approaches like at-speed testing, delay testing, IDDQ testing and low voltage testing. These are test strategies that are used in conjunction with standard functional and structural test. These test approaches also require an understanding of automatic test pattern generation (ATPG), since one must generate vector sets to catch these problems. Defect-based testing also is critical for failure analysis troubleshooting activities. Defect diagnosis uses these concepts and test techniques to help automatically detect defects.

Presentations

Introduction to Defect-Oriented Testing

This section provides an overview to defect-based testing. It explains how defect-based testing differs from standard test techniques and why it should be performed.

ATPG Basics

This section introduces the concept of Automatic Test Pattern Generation. It covers pseudorandom and deterministic patterns. It also covers ATPG program flow and the search problem associated with ATPG.

ATPG Algorithms

This section covers the mathematical basis of automatic test pattern generation routines. It includes information on the D-Algorithm, Branch and Bound techniques and heuristics.

CMOS Defect Mechanisms and Detection Overview

CMOS ICs exhibit particular responses to defects. Defects such as particles, mask defects, and etching problems can cause the IC to malfunction. This section covers the basic defects found on ICs and discusses their implications on the operation of the IC.

CMOS Opens and Detection Techniques

Open circuits exhibit particular behaviors in CMOS ICs. They can range from stuck-at behavior to more complex, time-varying behavior depending on the location of the open, the topology of the circuit and the circuit design itself. This section covers the behavior of open circuit defects, the methods used to detect these opens, and discusses the basic fault models associated with them.

CMOS Shorts and Detection Techniques

Short circuits exhibit particular behaviors in CMOS ICs. While most shorts will elevate current, the functional behavior can be more complex to understand. This section covers shorts, how to model them, and how to best detect them with both current and voltage-based techniques.

Defect Classes

This section covers defect classes and the electrical behavior of these defect classes. We concentrate on the bridging defect class, the delay defect class, and the open defect classes.

Detection Techniques for CMOS Defects

This section briefly covers the voltage and current techniques used to detect defects. It also discusses the nature of defects on test and reliability.

Failure Mechanisms in CMOS IC Materials

This section covers some basic information about failure mechanisms. We concentrate on CMOS defects, since CMOS is the most complex technology from a test standpoint. We also briefly discuss issues associated with process variations.

Parametric Defects and Detection Techniques

Parametric defects are becoming more common as chip designs move into the nanometer scale. Slight variations in the process lead to parametric defects that fall just outside of the intended operational range of the IC. There may be no defects present, but the circuit doesn't work as intended. Parametric defects require special test strategies, and a coordination between design and manufacturing. We discuss this issue in more detail in this section.

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Test Basics

This material covers basic issues in test. Currently, this course contains an introduction to automatic test and an overview of boundary scan test techniques.

Presentations

Automatic Testing Overview

This section introduces the concept of automatic testing of integrated circuits. It provides an overview of why testing is performed, and the equipment used to test ICs.

Boundary Scan Overview

This section introduces the boundary scan standard (IEEE 1149.1). It explains the use of boundary scan and discusses the ports, the test access protocol and the basic state diagram for the controller.

Test Engineering Overview

Test Engineering Equipment

Analog Design for Test - Overview

Continuity Testing

Current Testing

Leakage Testing

Digital Design for Test

Loadboard Hardware Components

Loadboard Hardware Design Flow

Test Economics

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Test Methodologies

This course material covers test methodologies for ICs. It includes information on digital testing, current testing, and timing tests. All three are useful to help localize defects and other problems on circuits prior to shipping them to the customer.

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Test Process Basics

Test process basics provides an overview of the test process and how defect-based test fits into it. This section covers the development of the test set from design through to production and the various components of test. It also discusses approaches such as random test pattern generation, and scan-based approaches for combinational and sequential circuits.

IDDx Testing

Quiescent Power Supply Current, or IDDQ testing is an important component of a test strategy for a complex IC. IDDQ, differential IDD, an time-based IDDQ measurements form the body of IDDx testing techniques. This section covers IDDx techniques in detail. It also includes discussion of techniques to use IDDQ with higher current ICs, a big issue because of today's thinner gate dielectrics and small feature sizes.

Low Voltage Test

Low voltage test is a less common test technique, but it has been shown to help detect some types of defects. Low voltage test operates on the principle that defect currents scale differently than transistor drives currents when the voltage is lowered. This can bring out potential defective conditions. This section covers this concept in more detail.

Timing Tests in Production

The most common, and most difficult, parametric defects to detect are timing problems. Timing problems require strategies such as varying the frequency of the IC under test, and changing the clocking signals in the scan circuitry. We discuss these techniques in more detail in this section.

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Design for Test

Design For Test, also known as DFT, encompasses a set of activities that designers normally do to help aid in the testing of ICs. Complex circuits can be quite difficult to test in a thorough manner, so engineers plan for the testing by designing the circuit in such a way so that the test engineers can achieve high test coverage with minimal test costs. DFT encompasses activities like design partitioning, the use of testable technologies, like low power static CMOS, the inclusion of scan circuits, the use of built-in self test or BIST, and other aids.

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Analog Design for Test - Overview

Analog DFT - Test Modes

Analog DFT - Other Methods

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Fault Models

This course material covers fault models that are used by engineers to develop test routines for complex chips. A fault model is an abstract concept designed to translate the behavior of a defect into a condition that can be tested, preferably on a digital test system.

Presentations

Fault Models for Defect-Based Test

This section introduces the concept of fault models, why they're needed, and for what purpose they're used. The section covers the four basic uses of fault models: test generation, fault simulation, quality prediction and fault diagnosis.

Bridging Fault Models

This section covers Bridging Fault Models and how to deal with various types of bridging possibilities in a circuit.

Delay Fault Models

Many defects in advanced CMOS ICs can be modeled with the delay fault model. Implementing the delay fault model can be quite challenging in a complex circuit. To that end, researchers have developed several approaches to both model delay faults and simplify the process of implementing tests for delay faults. These models include the transistion fault model, and the gate delay, path delay, line delay, and segment delay fault models.

Fault Diagnosis Algorithms

Fault Diagnosis Algorithms are the basis of Automatic Test Pattern Generation. Because of circuit complexity, computer-generated patterns are preferred over manual pattern generation. Algorithms operate on the chip design information using models such as the stuck-at fault model to create a test pattern. Algorithms discussed in this section include the D-algorithm, PODEM, FAN, pseudo-random algorithms, weighted algorithms, and more.

Fault Dictionaries

Fault Dictionaries are an alternate means to retain information about electrical faults on ICs. A Fault Dictionary is a database of some or all of the faults that can occur in an IC. The dictionary can then be used in conjunction with a test program or strategy to localize the problem on the circuit. In a complex IC, this dictionary can be quite large, so various strategies are used to compress the it, or divide it into sections using boundary scan. This section covers Fault Dictionaries and related techniques in more detail.

Stuck-At-Fault Testing

This section briefly describes the stuck-at fault model and how it works. It also provides a simple example and a discussion on how to create a computer algorithm based on the concept.

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Yield

Introduction

This material covers the topic of Yield Analysis and Modeling. Yield is a critical aspect of the semiconductor manufacturing process. High yielding components are necessary for profits and success at Foundries as well as the Integrated Device Manufacturers. This material covers the Principles and Procedures of Yield Analysis, Yield Analysis Techniques, Yield Modeling, Data Mining, and Yield Enhancement Techniques.

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Yield Calculator

This calculator calculates yield based on the Murphy yield model. It only considers die area (length) and the number of processing levels.

Yield Estimator

This calculator provides a more comprehensive way to calculate yield based on various processing factors.

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Models

Models are an important component of the yield analysis problem. We need models to predict not only the yield of new products, but also provide clues as to what types of problems might be occurring with a wafer lot or group of lots. This course covers general models for yield like the Poisson Yield Model, the Seeds Model and others. It also covers various techniques and approaches to predicting yield based on measured electrical and physical parameters.

Presentations

Introduction to Yield Analysis

This section provides an overview of yield analysis. The terminology, goals, and approaches to yield analysis are introduced. We also give several examples of some basic yield analysis problems, how they were addressed, and how they were resolved.

Advanced Yield Modeling

Advanced Yield Modeling covers yield modeling techniques that provide additional granularity in the overall yield of a product. This body of knowledge is sometimes called integrated yield management. Comparing parameters using a scatterplot can be challenging. Data interpretation can be quite difficult. The idea behind integrated yield management is to tie processing parameters to yield by reducing the data to a more simplified format, making graph interpretation straightforward.

Basic Yield Models

This section covers basic models used to predict the yield for a die given a particular size and defect density. This includes models like the Price Model, Seeds Model, Bose-Einstein Model, Murphy Model and others. We discuss the advantages and disadvantages of each.

Critical Area Analysis

This section covers methods to predict where defects might adversely affect the operation of a chip, resulting in yield loss. These methods provide a more accurate estimation of yield, but require extensive computer processing on the layout information to derive this more accurate number.

Data Mining Statistics and Plotting

This section covers covers basic statistics used in yield analysis scenarios. We cover how one turns generic data into histogram format, the normal distribution and lognormal distribution, and we discuss the chi-square goodness of fit for data. We also discuss various methods for displaying data, including normal plots, lognormal plots, scatter plots, and box plots.

Defect Analysis and Yield Loss

This section covers defects and their impact on functionality. Normally, defect analysis includes determining the probability that the defect will occur, and the probability that it will cause a failure in chip operation. The former probability is usually referred to as the defect density, and the later probability is usually referred to as the kill ratio. We explain how to determine which problems should be addressed first based on kill ratios and defect densities.

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Procedures

This course material covers the procedures associated with Yield Analysis. We cover procedures and methods that are used to help improve yield. These can be techniques used at the design level as well as techniques to address yield problems that are currently occurring.

Presentations

Yield Analysis Principles and Procedures

This section covers the high level principles used in yield analysis. We also spend time discussing the procedures from a general perspective. This includes the general approach, data-gathering phase, fault localization, electrical characterization, and analytical characterization activities.

Yield Analysis Tools and Techniques

Yield Enhancement Techniques - Proactive

This section covers proactive steps to improving yield. We cover design techniques that are used in the industry to reduce the probability of defects causing problems in the layout. We also cover design techniques that reduce sensitivity to process variations, and sub-wavelength lithography issues.

Yield Enhancement Techniques - Reactive

This section covers reactive steps to help restore or improve the yield of an existing line. We cover triage approaches, as well as techniques for identifying random defects and systematic defects. We also cover yield ramp up activities and product monitors. Last, we cover kill ratios and how to use the information to address yield problems.

Yield Methods for Low Volume Manufacturing

Yield improvement is a challenging activity in a low volume manufacturing environment. The ability to run experiments on wafer lots and gather data is limited. Furthermore, the data is limited to make judgments on yield changes. The best approach is to study the wafer lots one does have in as much detail as possible, and generate as much data as possible for each wafer lot. We discuss these approaches, as well as increased use of test structures and product monitors.

Root Cause Analysis

This section covers the techniques used to identify the root cause of failure. This section includes definitions, general principles, the basic procedure, and information on a number of specific root cause analysis techniques. We include information on 5 Whys, FMEA, Fault Tree Analysis, Fishbone Diagrams, Cause Mapping, Apollo Root Cause Analysis, and more.

Outlier Screening

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