In this article we will discuss the technology associated with source/drain regions on transistors, now commonly called source/drain extensions.
The choices for source/drain extensions are primarily based on the needs of the application. Different technologies require different features. For example, memory requires low leakage, long retention times, high density and low costs. Logic requires performance, and therefore higher drive currents. This needs to be balanced against a need for minimizing short channel effects, hot carrier effects, maintaining low resistances and capacitances, and minimizing leakage in low-power devices. Analog requires special attention to reducing the reverse short channel effect, the ability to match transistors to one another, and maintaining low leakage and noise.
Let’s begin by discussing the lightly doped drain region or LDD. The LDD provides a region that is lighter doped than main source/drain implants. It helps to reduce the peak-field at the drain boundary, which in turn reduces impact ionization, substrate, and gate currents, and hot-carrier generation. It also reduces gate-induced drain leakage and drain-induced barrier lowering. There is an improved control of the effective channel length. However, if the LDD is too lightly doped, it merely extends the channel and is ineffective in reducing the peak electric field. The peak field occurs near the light LDD and heavily doped drain boundary, or the N-/N+ junction. The optimal LDD extension concentration is in the 1018 – 1019 atoms per cubic centimeter range.
Another common component of the source/drain region is the angled halo, or pocket implant. This is typically applied to the NMOS transistor. The angled implant locally raises the channel doping below surface next to the source/drain region, leaving most of channel region to be more lightly doped, reducing the variability and the field in the device. Halo implants improve short channel effects and raise the punchthrough voltage while minimizing the impact on the threshold voltage and the body effect where the gate control is weaker. The angled implant can be done before or after the spacer etch. The tilt angle ranges from 7° to 60°, depending on the application. For ultra-short channel transistors, halo implants will require a very low thermal budget, that one would normal achieve with a spike, or flash anneal.
Stay tuned for the conclusion of this article in October!
Laser Voltage Imaging (LVI) shows the physical locations of transistors that are active at a specific frequency. LVI can be tuned to frequencies to be traced, and may also be used to show where to get the best signal strength for specific waveform measurements, and to the pixel where the "sweet spot" for probing is found. The Laser Scanning Microscope visually maps locations of transistors. By concentrating on a specific area of the DUT, one can scan for the dominant frequencies. LVI locates the transistors and thus maps circuits operating at those frequencies. LVI also enables signal tracing through circuitry, and even non-periodic signals can be monitored. This approach can also be used with Time-Resolved Light Emission.
Q: What types of techniques can be used to highlight bond pad cratering?
A: One technique that can highlight bond pads for cratering using an optical microscope is nickel decoration. The aluminum bondpad is etched away, and the chip is placed in a nickel plating solution for several minutes. The nickel will first adhere to the cracks, providing contrast in the optical microscope.
(Click on each item for details).
Failure and Yield Analysis on October 3-6, 2011 in San Jose, CA, USA
Semiconductor Reliability on October 11-13, 2011 in San Jose, CA, USA
Photovoltaics Technology and Manufacturing on October 20, 2011 in San Jose, CA, USA
Failure and Yield Analysis on October 31 - November 3, 2011 in Singapore
Semiconductor Reliability on November 8-11, 2011 in Singapore
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