In part 3, the final part of our Ion Implantation series, we will discuss some process monitoring and characterization issues. The major issues include doping process control issues, in-line monitoring and mapping tools to diagnose problems, and offline characterization techniques to look at the results of an implant, or a series of implants and thermal steps.
There are a number of process control issues that affect ion implantation. We list some of the more common issues here. Total implanted dose must be closely controlled for many applications. The dopant profile is also important. One must pay careful attention to the surface concentration, the peak concentration, the implant depth, and lateral distribution effects that are caused by shadowing of overlying structures and thermal diffusion. Another key issue in nanometer-scale ICs is uniformity across the wafer. One needs to examine this problem at both the macro and microscale. Closely related is wafer-to-wafer and day-to-day repeatability of the dose. The equipment must be precise for each wafer and for each run.
Contaminants are another important issue. Particles can locally shadow or interact with ion implantation, causing problems. The ion beam can sputter material, causing dopant cross-contamination, or introducing metals into the silicon, which can impact device performance. Beam purity is important. We want a consistent energy beam without lower or higher energy tails. Residual crystal damage can lead to leakage and other device performance issues. And finally, dopant activation is important. We want dopant atoms on lattice sites to create proper semiconductor action. If they remain as interstitials or as clusters, they do not produce the desired electrical behavior.
Characterization is an important aspect of monitoring the ion implant process. This can be done with electrical or physical tools. Four-point probe to measure sheet resistance of implanted layers is an important technique because it is fast and can be done inline with the process. This is the method of choice for monitoring medium and high dose implants. A material’s bulk resistivity ρ is defined by this equation,
where n is the number of charge carriers, e is the elementary charge of the electron, and μ is the mobility of the charge carriers. The sheet resistance of a uniformly-doped layer of thickness t is ρ over t. The units of RS are ohms per square.
For a non-uniformly-doped layer, like a diffused layer or an implanted layer that has undergone an anneal or high temperature event, the sheet resistance is the integral of the local sheet resistance at each point in the depth z, where z is the layer thickness (see equation below).
To make a four-point probe measurement, first contact the implant or structure of interest with an array of four co-linear probes, apply current across the two outer probes, and measure the voltage drop across the two inner probes. If the probe spacing is equal, and if z is much larger than a, then the sheet resistance can be reduced to the value
Another in-line measurement tool is the Modulated Optical Reflectance Probe, like the KLA-Tencor Therma-Probe. A modulated argon pump laser generates thermal waves in the silicon wafer, propagating temperature oscillations in thermally conductive material like silicon. The wave propagation is perturbed by lattice disorder, which could be implant damage. This causes local changes to the optical properties of the silicon surface. A helium-neon probe laser measures the net modulated optical reflectance signal, which is correlated to amount of damage. The correlation curves relate implant damage to implant dose. This is the method of choice for monitoring low doses. However, there are several important limitations. First, it is a very indirect measure of dose. The implant damage is a function of not only dose, but of other variables like energy, dose rate, beam spot size, and self-annealing. Another type of tool that can be used for in-line monitoring is the Wafer Surface Scanner. It is primarily used for particle or defect monitoring, but can resolve some implant damage effects.
Let’s move on to offline characterization techniques. Since they are primarily destructive and time-consuming, they are done less frequently. They are primarily for characterization but also used for periodic monitoring. The first one is Secondary Ion Mass Spectroscopy or SIMS. It is used to measure dopant profiles in semiconductor devices. The primary ion beam sputters through the implanted layer at a known rate, and the amount of ejected dopant is measured. The technique measures chemical concentration, not carrier concentration. It is also useful for confirming the presence of known or suspected contaminants, if they’re present in large-enough amounts. The second technique is Time-of-Flight SIMS or TOF-SIMS. This technique is used for shallow implants and surface analysis. The primary ion beam is pulsed in the nanosecond range; the secondary ion time-of-flight to detector will be a function of the ion’s mass. A separate sputter beam is required to advance to the next depth.
Another offline technique is the Transmission Electron Microscope or TEM. It is used to check for residual crystal damage. A focused electron beam passes through a very thin sample, and produces an image based on the electron interaction with the sample due to differences in elements or crystal orientation. It is capable of atomic resolution. Another technique is spreading resistance probing, or SRP. It is used to measure dopant profiles. In order to accomplish this, one must bevel a large-area structure and measure the resistance stepwise across the bevel. The carrier concentration can be computed from measurements of the resistance.
A final offline characterization technique is the charge monitor. It is used to measure charge build-up on a wafer during the ion implantation process. One can use a range of capacitor, EEPROM and MOS test structures. The most popular structure is a EEPROM structure known as CHARM2. The structure uses large metal charge collection electrodes or antennae tied to the control gate of a EEPROM transistor. Electrodes tied to the silicon through polysilicon resistors measure the net flux. One can then infer voltages and currents on the wafer surface from the threshold voltage shift.
Finally, let’s discuss some new techniques. A popular technique for ultra-shallow junctions is to use cluster boron beams. The basic idea is to implant a boron-based molecule that is much heavier than elemental boron, like octadecaborane. This yields much higher beam current for heavier doping and a factor of twenty better control over the projected range of the boron. It helps to overcome problems like beam blow-up during acceleration and transport, beam neutralization during deceleration and low beam current instabilities. It also gives sharper implant profiles because of its self-amorphization. It can be implemented with a relatively simple modified source design, and the technology is adaptable to other species like arsenic and phosphorus.
This section provides a brief overview of solid immersion lenses.
We will discuss the rationale for their use. Next, we’ll discuss the historical development of these lenses. We discuss their construction, followed by some of their applications in imaging and failure analysis.
The main reason for using a solid immersion lens is to increase spatial resolution. A simplistic way to think about a solid immersion lens is that it acts like a magnifying glass on the circuit. Solid immersion lenses are used to image from the backside of the silicon. This can be advantageous since silicon limits the wavelengths of light through the backside of the silicon to approximately 1.1 microns. With transistor gate lengths approaching 20nm, the size of the source/drain regions is now less than 100nm. In order to distinguish between transistors, we need a technique that not only allows light to pass through the silicon, but also to provide enough resolution to see these structures.
Much of the early work on solid immersion lenses was done at Boston University by Stephen Ippolito, Selim Unlu, and Bennett Goldberg. They first demonstrated the technique for imaging in 2000. In 2003 they showed the technique for failure analysis purposes, and shortly thereafter a number of semiconductor manufacturers began using SILs for their analysis work. Some used separate SILs, while others machined SILs or SIL-like structures into the backside of the silicon. By 2005, companies like DCG Systems and Hamamatsu were offering SILs with their optical probing tools. Today, most companies analyzing leading edge ICs use SILs in their equipment. There are now more than 30 publications on this technology, and there is likely to be more in the near future as this is still an active area of research.
There are three basic types of SILs: standard hemispherical SILs, aplanatic SILs, and Super SILs. This figure shows an example of a standard hemispherical SIL. The hemispherical shape of the SIL improves the collection efficiency of the light. It also introduces a magnification factor of n, where n is the index of refraction of the SIL.
The figure below shows an aplanatic SIL. First, we need to define aplanatic. The aplanatic point or plane is the location at which the light can be focused without any aberration. In an aplanatic SIL, the focal point of the light rays is not at the interface between the SIL and the IC die, but rather at a point within the die. The change in index of refraction between the SIL and the die causes the light to be bent to a new focal point. If the die is thinned appropriately, or if a mount is used, one can tailor the focal point to the active surface of the die.
The Super-SIL is a third type of SIL where the lens is polished flat to a point that permits the light to focus on the feature plane of interest -- in this case, the active surface of an IC prepared for backside analysis. Because the focal point is within the IC die, the light rays are significantly below 90 degrees, allowing more light to be captured. In a standard aplanatic SIL, light near the edge of the hemisphere is lost due to reflection, as it is close to 90 degrees.
Researchers are working on methods to improve solid immersion lens technology through the use of alternate lens materials, like gallium arsenide and sapphire, as well as combining SILs with other light technologies like polarization and iodization. For further reading on this topic, there is an excellent review article by Serrels et. al. in the 2008 Journal of Nanophotonics.
Q: Is there a way to do a selective wet etch so that only a portion of the chip is etched?
A: Yes there is. You can deposit photoresist, selectively expose it, develop it, and then etch in the area or outside of the area, depending on the type of photoresist used. The paper that discusses this technique is called "Micro-Control of Photoresist Deposition for Failure Analysis of Microelectronic Circuits" presented by K. Hussey, N. Dickson and J. Reyes at ISTFA in 1992.
Please visit http://www.semitracks.com/courses/packaging/copper-pillar-technology-and-challenges.php to learn more about this exciting course!
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Semiconductor Reliability on May 14-16, 2012 (Mon.-Wed.) in Munich, Germany
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Reliability and Characterization Challenges on June 11, 2012 (Wed.) in San Francisco, CA, USA
Copper Wire Bonding Technology and Challenges on July 11-12, 2012 (Wed.-Thurs.) in San Francisco, CA, USA
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