This article provides an overview of copper pillar technology and discusses some of the challenges.
Copper pillar bumping has become more common in the past couple of years for several reasons. One financial reason is the increased cost of gold for wire bonding. However, that can be solved through standard copper wire bonding. A more important reason is that copper pillar technology promotes a fine pitch, flip chip process, which is vital for today and tomorrow’s portable devices. Copper pillar bumping enables Thru Silicon Vias (TSVs), face-to-face bonding, and chip-on-chip bonding configurations that allow the manufacture of high-density electronic components.
Figure 1 shows an example where copper pillar bumping enables 3-D integration and packaging. In this example, the silicon interposer is attached to the package substrate using copper pillar bumps. TSVs through the silicon interposer bring signals to the active dice on top.
Copper pillar bumping is intended as a replacement to traditional solder bumping. While solder bumping is a lower cost process than copper pillar bumping, it doesn’t allow for the density and current capacity afforded by copper pillar bumping. Because of their lower resistance, they don’t heat as much as a solder bump, reducing electromigration issues. This permits higher densities; copper pillars can be utilized on pitches of less than 400 microns as well as in wafer level chip scale packages. Copper pillars also afford superior power management, both thermal and electrical. Lower resistances mean less heating in the pillars and less voltage drop within each pillar.
Copper pillars can be held to the substrate more securely through the use of an underfill. The underfill is applied as a non-conductive paste in the open areas between the pillars. The chip is then placed onto the substrate and the underfill is snap-cured. The coefficient of thermal expansion of the underfill pulls the chip to the substrate more than the copper pillar bumps, placing them in compression. Figure 2 shows the deformed tin-silver cap on the copper pillar that results from this process.
Copper pillar technology can be used on small dice in small packages like quad flat no-lead, or QFN, packages, on medium dice with the pillars providing connection to a laminate substrate, and on large dice mounted on fine-pitch laminate substrates.
For small dice, copper pillars can be used with no underfill in injection-molded components like QFN and Thin Small Outline Packages, or TSOPs. The connections can be made using solder materials with no-clean fluxes. For medium and large-sized dice, underfills with flux are required to stabilize the stresses between the die and the substrate. The underfills can use capillary action and can be reworkable or non-reworkable.
Here is an example of a small die in a flip chip on lead, or FCOL, package. The copper pillar is mounted to the bond pad, and the die is flipped upside down and mounted to the copper leadframe with a reflowable tin solder.
Copper pillar bumps are now commonly used on QFN packages. They provide benefits for high-speed circuits, including improved co-planarity and heat dissipation. QFN packages do not have gull wing leads that act as antennae, creating noise in high frequency applications. The electrical performance is also better than traditional leaded packages.
For large dice, Intel, Amkor and Texas Instruments have all released products that use fine pitch copper pillar bumps. These devices have utilized more than 200 I/O connections. These manufacturers have primarily used no-clean fluxes.
Copper pillar bumping is now being used in microprocessor applications as well. The advantages are a similar to those of other components; one can achieve superior electrical performance, improved thermal management, and implement this with a lead-free solution.
Figure 4 helps to illustrate the micro-bumping process. This is a process that facilitates die-to-die bonding. Copper pillars are attached to both dice, with tin solder applied to one of the die. In this example, we show it applied to the flipped die. The dice are brought in contact with one another and then subjected to reflow. The solder is consumed, as well as a portion of the copper pillars, forming an intermetallic compound that provides the mechanical and electrical connection.
The materials used for copper pillar bump assembly vary from company to company. Most manufacturers are experimenting with no-flow underfills, no-clean fluxes, and pre-plated leadframes (typically nickel-palladium-gold) to provide both manufacturability and reliability improvements.
Let’s focus on the flux issue for a moment. Ultrasonic cleaning is a popular method for the cleaning of flux residue. In fact, ultrasonic frequencies around 40 kilohertz work great for cleaning flux residue from stencils and bare boards. However, applying the frequency for a longer time period, or using lower frequencies may cause damage to certain components when a board is populated. This has lead to the use of multisonic cleaning where a combination of frequencies is used to reduce damage. Therefore one must be careful of how frequencies are applied for cleaning. One phenomenon that occurs during ultrasonic cleaning is micro-bubble cavitation. However, decreased bump height and copper pillar heights cannot be cleaned as easily since the ultrasonic wavefronts cannot penetrate the smaller features. The smaller features are also more susceptible to damage, since lowering the energy reduces the cleaning capability. This involves tradeoffs in time, ultrasonic energies, and ultrasonic frequencies.
Scaling has introduced several problems with flip chip bump scaling. One issue is intermetallic compound formation. As the solder bumps scale down the intermetallic formation does not. This leads to situations where all that remains of the solder joint is the intermetallic compounds. Voiding can lead to weak mechanical and higher resistance pillars.
Another source of reliability problems with copper pillar bumping is with the thermomechanical stress inherent in the package. These forces introduce stress into the interconnect layers on the IC. Copper has a different coefficient of thermal expansion than the die, which leads to these stresses. Figure 6 shows how those stresses manifest themselves in the vicinity of the copper pillar. The red regions indicate high stress levels.
In conclusion, copper pillar bumping is likely to increase in the future as a packaging technology. The superior resistance properties of copper allows for smaller bumping pitches, and improves electrical and thermal performance on these circuits. Although thermomechanical stresses are a concern as well as the processing constraints that surround copper wires and pillars, the advantages outweigh the problems. Expect to see this technology more in the future.
Most people working in semiconductor reliability positions are aware that alpha particles and neutrons can lead to single event upsets. Alpha particles are generated by contaminants and radioactive materials in both plastic and ceramic packages, and solder bumps. They can also be generated by neutron collisions with silicon, and with boron-10 in borophosphosilicate glasses. Another particle though that is less known for upsets is the muon (μ). Muons are sub-atomic particles that can be either positively or negatively charged (μ−, μ+). They have a mass of approximately 200 electrons, and a lifetime of approximately 2.2µsec. Low energy muons with energies of 0.5 to 1.0 MeV can generate significant charge within an integrated circuit. Unlike neutrons that infrequently impact the nuclei of other atoms, muons generate charge carriers through the electromagnetic force. If the technology feature sizes allow for the collection of that charge, the integrated circuit can experience an upset. So even low muon fluxes can significantly add to the single event rate for sensitive devices. Figure 1 below shows simulated muon kinetic energy distributions, as seen on the front of the part, corresponding to experimental momenta including upstream energy losses and straggling on the bottom part of the figure. Experimental error counts for 65 nm, 45 nm, and 40 nm SRAMs versus estimated muon kinetic energy at 1.0 V bias on the top part of the figure. The dashed horizontal line represents an approximate muon-induced SEU cross-section for reference.
This problem is likely to increase in the future as we scale to smaller devices since the charge volumes decrease. Many researchers believe muons will become a more significant contribution to single event upsets at the 32nm node and below.
Q: Can etching of the polyimide layer to form windows for the bond pads on a circuit subsequently create poor contact for bond wires?
A: Yes, this has been observed in the past. The etch residues and hydrolysis products affect the surface of the bond pad, degrading its adhesive properties. An early paper that discussed this problem is C.G. Shirley and M.S. DeGuzman, "Moisture-Induced Gold Ball Bond Degradation of Polyimide-Passivated Devices in Plastic Packages", Proc. IRPS, pp. 217 - 226, 1993.
Please visit http://www.semitracks.com/courses/reliability/semiconductor-reliability-and-qualification.php to learn more about this exciting course!
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Reliability and Characterization Challenges on June 11, 2012 (Wed.) in San Francisco, CA, USA
Copper Wire Bonding Technology and Challenges on July 11-12, 2012 (Wed.-Thurs.) in San Francisco, CA, USA
Introduction to Polymers and FTIR on August 16-17, 2012 (Thurs.-Fri.) in San Jose, CA, USA
Failure and Yield Analysis on August 27-30, 2012 (Mon.-Thurs.) in San Jose, CA, USA
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