In this article we will discuss a failure mechanism that has been around for as long as the semiconductor lithography process – the mask defect. To focus our discussion, let’s take a specific type of masking defect, the diffusion masking defect. A random diffusion defect can cause areas of extra diffusion or missed diffusion, associated with the photo masking process. It often results in a wide range of device level problems including leakages between diffusions, open resistors, and faulty transistors, which cause functional and parametric defects. Any defect on the mask or pellicle, which alters the pattern, such as a scratch or contaminant, can cause these issues. It may also be caused by a defect in the patterned photoresist from scratches, or particles in, on, or under the resist.
The anomalous pattern may or may not be apparent from visual inspection. In many semiconductor technologies, diffusion and implant defects are normally not visible because photoresist, rather than oxide, serves as the mask. Therefore, there is no imprint of the mask after the resist is removed. Almost all CMOS and many junction isolated bipolar processes strip and regrow the oxide layers after the isolation or base implant or diffusion steps and obscure defects at prior masks. However, when viewed in cross-section, the effects of the particle are still present. The defect may still be detected by a slight depression in the silicon (from silicon consumed during oxide growth) or a slightly different oxide thickness (from oxide growing faster over more heavily doped regions). Similarly, the mask which opens oxide holes for the source, drain, or emitter implant or diffusion will obscure base masking defects that might be present under the emitter. For instance, a pinhole defect in a negative resist base photo mask will leave a spot of oxide inside the base diffusion opening and will create a location where base dopant is blocked. If this defect is in an area designated to be an emitter, the subsequent emitter oxide opening step will remove the residual base oxide and make it difficult to spot the defect visually.
Figure 2 shows the random diffusion masking defect failure mechanism. A random diffusion-masking defect can cause areas of extra diffusion or missed diffusion associated with the photo masking process. It can result in a wide range of device level problems, including leakages between diffusions, open resistors, faulty transistors, causing functional and parametric defects. It can be caused by any defect on the mask or pellicle which alters the pattern, such as a scratch or contaminant. It may also be caused by a defect in the patterned photoresist from scratches, or particles in, on, or under the resist.
The figure is helpful in establishing the effect of different defects on the finished IC. Emitter, base and contact masks (negative resist) tend to be mostly transparent with dark rectangles where the dopants or contacts are to go. With positive resist there are clear boxes on an opaque background. The isolation mask for negative resist resembles a web of connected black lines separating the clear epi tubs. For positive resist the opposite is true, clear isolation diffusions surrounding opaque epi tubs. The metal mask for negative resist is clear where metal belongs. For positive resist the metal pattern is opaque on a clear background.
For each of these types of layers it is possible to create a table which will reveal the likely effect on the circuit of a wide range of defects. We show some typical results in the table below (Table 1).
Diffusion masking defects are as stable as the intended diffusions and do not normally pose a reliability risk. The primary risk is that, by putting random elements into the circuit, they alter the circuit operation in ways which may or may not be caught by the outgoing ATE test equipment. The vast majority of diffusion masking defects are weeded out at wafer probe or sort. Particles in, on, or under the resist can interfere with its exposure or development leading to extra or missing resist on the wafer and subsequent additional or missing diffused areas. Scratches or smearing of resist similarly add diffusion where none was intended or block it where it was. Missing or extra opaque areas on the photo mask have similar effects. Early technology required the photo mask to physically contact the resist coated wafer. Crystal defects, such as epi spikes, created high spots on the wafer, which damaged the photo mask at that location and caused subsequent prints from that mask to replicate the same defect on each subsequent wafer, causing "repetitive masking defects". As the technology progressed to projection alignment, the mask never comes into contact with the wafer, and is typically encased in a plastic shroud called a pellicle, which protects the mask surface from dust and damage. Any dust landing on the plastic surface is several mm away from the mask pattern and is so out of focus during the printing process that it will not be replicated on the wafer resist pattern. Because projection masks are so well protected they have an unlimited lifetime and great expense can be taken making them perfect using e-beam lithography, defect inspection and correction using Focused Ion Beam tools. As device dimensions shrunk and wafer diameter increased it was increasingly difficult to print the whole wafer in one exposure. Reducing steppers have a 4-5x larger pattern on the mask, which is optically reduced and stepped across the wafer in several exposures. If the reticle did have a masking defect that defect would be repeated in each field printed. Also, because each field is separately aligned the alignment may vary from field to field. Fields are generally a few cm on a side.
This technical tidbit helps explain the difference between ATPG and ATPG Diagnosis. ATPG Diagnosis uses the ATPG circuitry, tester, and test results to help isolate the location of a failure on a complex chip.
It is important to differentiate between “ATPG” and “ATPG diagnosis”. Not just because the actual pattern generation and the diagnosis of ATPG patterns may be performed with different tools/products, but because there are some subtle, but important differences. For instance, during pattern generation, you may, for instance, only target stuck-at faults, since a pattern targeting stuck-at faults will typically detect bridge and open defects. For diagnosis, however, you would typically also have models for bridges and opens, even though these models weren’t needed for pattern generation. Therefore, ATPG diagnosis typically involves additional test engineering effort after the failure is discovered by testing.
Here’s how the process works. During the design phase, design and test engineers run automatic test pattern generation software to generate test vectors that will theoretically exercise the majority of the nodes within the circuit. These patterns can be input into a tester. The tests can be run on a part or group of parts to identify failures. These failures can then be analyzed for trends or severity. If the production contract or other issues dictate that the parts should be analyzed, they can be run through an ATPG-based diagnosis process. With models for opens and bridges, one can use ATPG-based diagnosis to identify suspect nodes based on the layout and failing vectors. One can make further use of the data for debug, failure analysis, and statistical analysis. Although this process can require more test engineering effort, ultimately it takes less effort than the requisite detailed failure isolation effort that is often required for analysis of complex ICs with subtle functional failure modes.
Q: Why do we typically use a lightly doped epi layer on top of heavily doped substrate?
A: There are several important reasons why p- epi/p+ substrate works well. One is to reduce the MOS leakage current. If we were to simply fabricate transistors in a p- substrate with no epi, there would be a higher concentration of minority carriers. As such, the carriers should diffuse for hundreds of microns to space charge regions and be collected as a reverse bias leakage current. This is particularly a problem at higher operating temperatures. However, if one uses a p- epi layer on top of a p+ substrate, the p+ substrate has few minority carriers, so the minority carriers would only be generated in the epi. This has the effect of suppressing the diffusion current and lowering the leakage (important for low power applications). In addition, the p- epi/p+ substrate reduces the possibility of latch-up; it helps getter or trap oxygen precipitates, and finally, the p- epi layer is more free of oxygen, so that helps prevent the formation of defects.
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