This year’s International Electron Device Meeting (IEDM) discussed a wide range of approaches for creating CMOS transistors with better performance. One axis of performance that is important is higher speed for faster switching. Higher speed invariably means higher mobility, so researchers have been investigating techniques to make this happen.
Silicon has a moderate mobility, but there are methods to improve it marginally. This can be done using strain. Companies like Intel and TSMC offer technologies and devices that use strained silicon. To get a larger improvement, one needs to consider alternate materials.
This table shows the major materials and candidates that can be or are used in CMOS devices. Silicon is the existing material for most devices. The electron and hole mobility for silicon are reasonable, but they’re not the highest numbers that are potentially available. Germanium has a much higher electron mobility and a lower electron mass. More importantly, germanium has the highest hole mobility of any of the major semiconductor materials at 1900 cm /V-sec. It also has the lowest mass for heavy holes, which is the main type of carrier in a p-channel transistor. Some companies, like IBM, mix Si and Ge together in the transistor channel to improve mobility. GaAs, InP, InAs, and InSb all have even higher mobilities. InAs and InSb have the highest mobilities, but the bandgaps for these materials are quite low. GaAs and InP have a larger bandgap, which makes them more useful in low power applications.
In order to create a channel with a different material, one must take into account the lattice mismatch. This chart shows the energy gap of several compound semiconductors as a function of their lattice constants. We also include germanium and silicon on the list. In general, germanium and the three-five materials have larger lattice constants than silicon. A high mismatch is worse for process integration as it is hard to control the strain induced by the differences in the lattice constants. Notice that germanium is about four percent larger than silicon. InGaAs is approximately eight percent larger, when deposited as a 53 percent indium, 47 percent gallium ratio.
Materials with a lower bandgap tend to have lower electron effective mass (high electron mobility) and higher permittivity. Since a narrow bandgap leads to high leakage current, it is necessary to choose appropriate materials from the viewpoint of both effective mass and bandgap. This means that materials like germanium and gallium arsenide are best positioned as alternate channel materials. However, this is only part of the story. Another factor for which one must account is the Schottky barrier height. The Fermi level position tends to be strongly correlated with the minimum in the interface trap density. The Schottky barrier height is also correlated to the interface trap density minimum. Therefore, one would prefer a material with a lower Schottky barrier height against electrons for an n-channel device, and a lower Schottky barrier height against holes for a p-channel device. Germanium is a suitable candidate for the p-channel device, but gallium arsenide is not as suitable. Better materials from a Schottky barrier standpoint would be indium arsenide, indium phosphide, or indium gallium arsenide.
In conclusion, there are a number of possibilities, but each possibility has advantages and disadvantages. Germanium is an excellent choice for p-channel transistors, as it has the highest hole mobility, minimal lattice mismatch, and a low Schottky barrier height against holes. GaAs is a mature technology, has a large bandgap (which means low leakage), and has a relatively low lattice mismatch, but it has a high Schottky barrier height to both electrons and holes. InP and InGaAs are both suitable for n-channel transistors as they have low Schottky barrier heights to electrons, but their lattice constants are quite different than silicon. InAs might also be suitable, but its bandgap is quite narrow, leading to higher leakages. GaSb might be suitable for p-channel transistors, but it has not been studied sufficiently yet. It also has a large lattice mismatch to silicon. InSb is yet another candidate that could be used in both p- and n-channel transistors, but the bandgap is very narrow and the lattice mismatch to silicone is quite large. At this time, germanium is the leading candidate to replace silicon in the p-channel transistor, and InAs or InGaAs are probably the leading candidates for the n-channel transistor, but new results could change the outcome. If the research continues to be positive, we should expect to see these materials used in transistors within the next 4-8 years.
Gallium nitride (GaN) is gaining traction as a material for high power semiconductor devices. Several manufacturers are now selling GaN devices for applications that require high power and high voltage, like military radar systems, blue LEDs for Blu-Ray players, and power inverters in satellites. As with all semiconductor devices, GaN suffers from various failure mechanisms. We can group failure mechanisms into two general areas: parasitic effects and degradation mechanisms. Parasitic effects include current collapse, excess leakage current, the Kink effect, and hot electron degradation. Common degradation mechanisms include gate leakage current, trap formation, gate metal diffusion and ohmic metal degradation. In this article, we’ll cover current collapse in more detail.
Current collapse manifests itself as a lag or delay in current through a transistor as the gate is switched on and off. The lag is primarily associated with the rise in current as the gate-to-source voltage goes high, rather than the fall in current as the gate goes low. This shows up as a slump, shown in Figure 1 on the upper right. The correct waveform is shown on the lower right.
Figure 2 shows experimental data that characterizes the current collapse effect. The degree of collapse is associated with the applied voltage to the gate. The higher the applied gate voltage, the greater the current collapse. The current goes down as a result of a change in threshold voltage and the decrease in transconductance. Current collapse is in general due to surface traps. One of the major differences between silicon and compound semiconductor-based transistors is the lack of a native oxide or dielectric in a compound semiconductor MOSFET. Since one cannot easily oxidize or nitridize the surface of a compound semiconductor, one must instead deposit a dielectric. In general, deposited dielectrics do not form a strong bond to the semiconductor material. This means that there are numerous dangling bonds that can lead to interface traps. A second interface can be problematic as well. Traps in the epitaxial region can induce a collapse through a threshold voltage shift. In order to create a high electron mobility transistor (HEMT), engineers grow aluminum gallium nitride (AlGaN) layers on the GaN to produce a quantum well, or channel that facilitates electron flow in the device. Like the deposited dielectric, this deposited semiconductor layer can have numerous dangling bonds due to processing and lattice mismatch effects. These dangling bonds can create traps which affect the threshold voltage, which in turn affects the current through the device.
To correct these problems, process engineers work to minimize trapping effects by ensuring optimal bonding conditions between the epitaxial layer and the substrate, and the semiconductor material and the dielectric. Process engineers experiment with temperature, pressure, growth rates, and other variables associated with Chemical Vapor Deposition to minimize the problem. This can help to minimize this parasitic effect. Another way to minimize the effect is to use a silicon nitride passivation layer. Silicon nitride has the advantage of containing nitrogen like the GaN and AlGaN layers, which leads to fewer dangling bonds.
Q: Currently, I have an issue with a BJT IC that failed after reliability. The failures recovered after we subjected them to baking. We did put these devices back into the chamber in the hope of simulating the failure again. But no failures were detected. You can say that baking has irreversible effect on these devices.
Do you think this is a case of surface charge? How can I confirm further if surface charge is the cause here.
Hope you can spare some time to help me with this issue.
Thanks a lot for your help.
A: It could still be a charge-related problem, but the charge may not have occurred in a way that a burn-in could activate. For example, an overstress event that avalanches the collector-base or emitter-base junction can sometimes place charge on a junction. If the bias is correct during the test, or if the overstress event occurred at the end of the reliability test during the electrical testing, then the charge might be present during the test. If you then did a bake, you would re-distribute the charge and make the leakage go away. If you put the devices back in the chamber, but there was no overstress event, there would not be any failures.
Examining the I-V curves and a schematic of the bias in the reliability test would also be a useful thing to do. It might give you some insight into where the overstress might have originated and how it might have been detected at electrical test.
Please visit http://www.semitracks.com/courses/processing/wafer-fab-processing.php to learn more about this exciting course!
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