Advanced Semiconductor Packaging and Technology

The drive to reduce costs in semiconductor and integrated circuits remains a key challenge for the industry. For example, many of today's ICs use expensive gold wiring. As a result, the industry is pushing to use copper wires and copper pillar bumping in an increasing array of applications. This has created a number of challenges related to the bonding and packaging of these components. Advanced Semiconductor Packaging Technology and Challenges Course is a 3-day course. The first day is an instructional session that details the advances in copper wire bonding technology. This session will explain the advantages and challenges of using copper wire as compared to the current gold wire standard. It will give details on new copper wire alloys currently being used as well as the reliability aspects associated with using copper wire. The course will also discuss new advances in silver (Ag) wire and the cost savings, use cases and potential issues seen when using silver wire with common IC assembly.

The second and third day sessions offer detailed instruction on the technology issues associated with today's semiconductor packages. We place special emphasis on current issues like bond formation, bumping, and package design and manufacturing processes. This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.

By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and where future package directions are headed. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.

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Cost

$1,695

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Please fax the printable registration form for public courses to us at 1-866-205-0713 to complete your order.

Additional Information

For dates and locations in South East Asia, please contact us at se-asia.courses@semitracks.com.

Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments:

  1. Basic Semiconductor Copper Pillar Bumping Metallurgy. Participants will study the manufacturing techniques used to create these packages as well as other common bumping methods used in semiconductor manufacturing today.
  2. Wafer Design Rules and Pillar Design. The course presents design concepts needed at the wafer and package level to ensure a successful package design. The Back-End-of-Line (BEOL) materials interact with the copper pillar and the copper pillar interacts with the package substrate. These interfaces need to be properly designed to ensure a reliable, cost-effective solution.
  3. Common Package Types. Participants will learn about the various package types on which on can use copper pillar bumping. This includes both molded packages like Ball Grid Arrays and Quad Flat No-Lead packages, as well as direct chip attach packages such as chip scale packages and package-on-package configurations.
  4. Reliability and Environmental Tests. The last part of the class brings together the basic principles and selected alloy systems to analyze the results of reliability testing, interpret the observed failure modes to identify root causes, and predict behavior for materials or process changes implemented to lower costs and/or improve reliability. The course covers moisture tests, thermomechanical tests, electro migration, and failure analysis methodology.

The course will also discuss the use of copper pillars in Through Silicon Via (TSV) formation in wafers as well as thin wafer handling. The course will also discuss and review the most common assembly and packaging techniques for TSV assembly and how copper pillars are further utilized to form the die stack interconnections on today's packages and die to die bonding.

Course Objectives

  1. At the end of the course, participants will understand the various types of copper pillar bumping techniques and technologies.
  2. They will also know about the manufacturing techniques involved in creating these packages.
  3. Participants should be able to predict and identify potential reliability problems and the environmental testing that can identify and bring these problems to the surface. They should also know how to interpret failure analysis results.
  4. Participants will learn methods that can be applied to process and material changes to lower cost and produce IC packages with higher yield and increased reliability.
  5. Participants will be able to make decisions about how to construct and evaluate new packaging designs and technologies.
  6. The participant will see several case studies associated with Copper Pillar Bumping and their use in a variety of package types including FC-BGA, WL-CSP, and TSV Die Stacks.

Course Outline

Day 1

  1. New evolution of Copper Bonding Wire
    1. Copper wire versus Gold wire
    2. Copper wire technical challenges
    3. Bonding process window comparisons
    4. Common problems bonding Copper wire in HVM
    5. Wire solutions to fine pitch bonding (Introduction of PCC wire)
  2. Palladium Coated Copper (PCC) bonding wire
    1. Wire making comparisons Copper vs. PCC
    2. Storage and shelf life comparisons bare Cu and PCC
    3. Introduction of next generation of PCC wire
    4. Hardness and compression FAB (free air ball) comparisons (Au/Cu/PCC)
    5. FAB EPMA mapping of PCC wire (Palladium distributions)
  3. Reliability Section for Copper wire
    1. Common failures of HAST and HTS
    2. UHAST and HTS reliability test and cross sections
  4. Plating overview on compatible surface finishes for Copper wire
  5. Introduction to Ag bonding wire

Day 2

  1. Wafer bumping process
    1. Solder Bumps variations and use
    2. Copper Wafer Bumping Methods
  2. Flip-Chip WLP Technologies with Conductive Adhesives (Lead-Free)
    1. Conductive Adhesives – ACA, ACF, etc.
    2. Au, Cu, NiAu, and Au-stud Bumps
    3. Materials, Process, and Reliability of WLCSP on PCB with ACF
    4. Au-Stud Bumped WLCSP with ACF on PCB
    5. Au-Stud Bumped WLCSP Diffused on Au-Plated PCB and Flex
    6. Reliability of Solderless Flip-Chip Assemblies
  3. Flip-Chip Wafer Level Processing Technologies
    1. Solder Bumps
    2. Wafer Bumping Methods
    3. Solder-bumped Flip Chip on PCB/Substrate Assembly Process
    4. Underfill Encapsulants

Day 3

  1. Solder Joint Reliability of Flip-Chip WLCSP Assemblies
    1. 3D IC Integration and WLP
    2. Embedded Wafer Level Packaging
  2. TSV Introduction
  3. TSV Processes
    1. (Etching or Laser Drilling, Dielectric Deposition, Barrier/Seed Metal Plating, Filling, Polishing
    2. Via First TSV
    3. Via Last TSV Thin Wafer Handling
    4. Low-Temperature Bonding (LTB)
  4. TSV package Types
  5. Q&A Session

Instructional Strategy

By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor packaging and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field.

Instructor Profiles

John Briar

John Briar

More than twenty years experience in electronics and manufacturing with duties including, President, Chief Technologist, and Director of Engineering focusing on new product, new process, and new market development in the area of Integrated Circuit (IC) packaging and test.

Part of the core start-up team that established the world leading IC packaging factories at STATS/Chippac in Singapore, Amkor Electronics in the Philippines, and Amkor/Anam Electronics in Korea.

Direct hands on development of all types of IC packaging technologies including wafer RDL and bumping, WLCSP, flip chip packaging, LGA/BGA large die stack packages with up to 16 die, and multiple die stack leadframe packages.

Wrote and awarded numerous U.S., Singapore, and other international patents and inventions relating to IC packaging. Published and presented a variety of technical papers worldwide and recognized expert in packaging worldwide. Received B.S.M.E. degree from the University of Central Florida in Mechanical Engineering and began working the same year in electronics packaging for Northern Telecom.

William (Bud) Crockett Jr.

Bud has over 18 years of international experience in start-up, emerging growth and high growth companies. Bud's career exposure encompasses both front end and back end NPI operations. His technical focus is in managing new product launch, material/package qualification and sustaining initiatives for the semiconductor industry with extensive experience in wire bond interconnects. His broad scope of responsibilities was focused in the APAC region and North America onshore pre-Asia production volume facilities.

His business development experience includes International licensees, strategic partnerships and alliances. Bud received a B.S. degree from Cal Poly State University in San Luis Obispo, California. Prior to receiving his degree, he proudly served in the US Navy for 8 years as weapons control radar systems.