The drive to reduce costs in semiconductor and integrated circuits remains a key challenge for the industry. For example, many of today's ICs use expensive gold wiring. As a result, the industry is pushing to use copper wires and copper pillar bumping in an increasing array of applications. This has created a number of challenges related to the bonding and packaging of these components. Advanced Semiconductor Packaging Technology and Challenges Course is a 3-day course. The first day is an instructional session that details the advances in copper wire bonding technology. This session will explain the advantages and challenges of using copper wire as compared to the current gold wire standard. It will give details on new copper wire alloys currently being used as well as the reliability aspects associated with using copper wire. The course will also discuss new advances in silver (Ag) wire and the cost savings, use cases and potential issues seen when using silver wire with common IC assembly.
The second and third day sessions offer detailed instruction on the technology issues associated with today's semiconductor packages. We place special emphasis on current issues like bond formation, bumping, and package design and manufacturing processes. This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.
By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and where future package directions are headed. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.
Add To Shopping Cart
Please fax the printable registration form for public courses to us at 1-866-205-0713 to complete your order.
Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments:
The course will also discuss the use of copper pillars in Through Silicon Via (TSV) formation in wafers as well as thin wafer handling. The course will also discuss and review the most common assembly and packaging techniques for TSV assembly and how copper pillars are further utilized to form the die stack interconnections on today's packages and die to die bonding.
By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor packaging and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field.
More than twenty years experience in electronics and manufacturing with duties including, President, Chief Technologist, and Director of Engineering focusing on new product, new process, and new market development in the area of Integrated Circuit (IC) packaging and test.
Part of the core start-up team that established the world leading IC packaging factories at STATS/Chippac in Singapore, Amkor Electronics in the Philippines, and Amkor/Anam Electronics in Korea.
Direct hands on development of all types of IC packaging technologies including wafer RDL and bumping, WLCSP, flip chip packaging, LGA/BGA large die stack packages with up to 16 die, and multiple die stack leadframe packages.
Wrote and awarded numerous U.S., Singapore, and other international patents and inventions relating to IC packaging. Published and presented a variety of technical papers worldwide and recognized expert in packaging worldwide. Received B.S.M.E. degree from the University of Central Florida in Mechanical Engineering and began working the same year in electronics packaging for Northern Telecom.
Bud has over 18 years of international experience in start-up, emerging growth and high growth companies. Bud's career exposure encompasses both front end and back end NPI operations. His technical focus is in managing new product launch, material/package qualification and sustaining initiatives for the semiconductor industry with extensive experience in wire bond interconnects. His broad scope of responsibilities was focused in the APAC region and North America onshore pre-Asia production volume facilities.
His business development experience includes International licensees, strategic partnerships and alliances. Bud received a B.S. degree from Cal Poly State University in San Luis Obispo, California. Prior to receiving his degree, he proudly served in the US Navy for 8 years as weapons control radar systems.