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March 15, 2015

Thermal Processing- Issues and Effects, Part 2

There are three major factors that affect the availability of the oxidizing species. They include diffusivity, solubility and pressure. In terms of diffusivity, oxygen diffuses much faster through silicon dioxide than water molecules. The water molecule, with its angled shape, occupies more volume than the oxygen molecule. This makes it more difficult for the water molecule to move through the silicon dioxide structure. On the other hand, water is approximately 600 times more soluble in silicon dioxide than in oxygen. Silicon dioxide readily traps and holds water, while oxygen tends to diffuse away quickly. Pressure is the third factor affecting oxidation. Increasing pressure from the outside environment increases the concentration of the species in the reaction zone.

This graph shows the effects of pressure on oxide growth in pyrogenic steam. The graph shows the oxide thickness as a function of oxidation time for several different pressures. Notice that the oxide growth rate increases as the ambient pressure is increased.

There are several factors that change the surface potential of the silicon surface. These are crystal orientation, silicon doping concentration, and surface treatment. The <111> plane oxidizes the fastest while the <100> plane oxidizes the slowest. The bonds coming out of the <111> plane more easily accept oxygen. Higher surface doping concentrations give higher oxidation rates. The silicon to silicon bonds are compressed and/or stretched by substitutional impurities. These bonds are more easily broken to accept oxygen than silicon to silicon bonds in an area where the lattice is free from impurities. Finally, surface treatments such as a hydrochloric acid treatment can increase the growth rate. The acid oxidizes the surface, allowing oxygen to bond more easily.

This graph shows the doping effects on oxidation. Notice that as the concentration of phosphorus increases, the growth rate of the oxide increases. The effect is more pronounced at lower temperatures. At higher temperatures, one can see that the oxidation lines are closely packed together.

This graph shows the effects of two different pre-treatments, and no pre-treatment of the silicon surface. The sulfuric acid – hydrogen peroxide clean oxidizes the surface, allowing faster oxide growth, while the ammonium hydroxide – hydrogen peroxide – water clean makes the surface more alkaline, reducing the growth rate.

This graph shows the effects of oxide growth when the silicon surface is exposed to hydrochloric acid. Researchers have studied the effects of chlorine gas on silicon dioxide growth for a number of years, since chlorine can reduce fixed and mobile charge in the silicon dioxide, increase the lifetime of the minority carriers, and reduce the density of oxidation-induced stacking faults in the silicon below. Chlorine can also cause the oxide reaction rate to increase, but the reasons for this are not well understood. Researchers have also observed the buildup of chlorine at the silicon/silicon dioxide interface.

May 1, 2011

Electronic Gun Configurations for Scanning Electronic Microscopes
By Christopher Henderson

The Scanning Electron Microscope is a basic instrument for analysis and characterization. We will cover the basic configuration of the electron guns in this article. Scanning Electron Microscopes (SEMs) fall into three basic configurations, Tungsten, Lanthanum Hexaboride or LaB6 and field emission. Within the field emission category, there are two basic configurations: the cold cathode configuration and the Schottky Emitter configuration.

Figure 1 shows the basics of a tungsten-based system. In a standard tungsten system, a bias is placed across the filament; the current through the filament heats it. At high temperatures, the material emits electrons, which can then be accelerated down the column. The high voltage power supply between the Wehnelt cylinder, filament, and anode plate determines the primary electron beam energy.

Figure 2 shows the basics of a lanthanum hexaboride system. Lanthanum hexaboride, also known as LaB6, emits a higher number of electrons than a tungsten filament, permitting higher quality images. In this gun configuration, a heating coil encompasses the LaB6 rod to heat it. As with the tungsten system, the high voltage power supply lies between the Wehnelt cylinder and anode plate to determine the primary electron beam energy.

Another method for generating electrons is the field emission gun. A schematic of a field emission tip is shown in Figure 3. When the cathode forms a very sharp tip (typically 100 nm or less) and the cathode is placed at a negative potential with respect to the first anode so that the local field at the tip is very strong (greater than 10 to the 7 Volts per centimeter), electrons can tunnel through the potential barrier and become free. Although the total current is lower than either the tungsten or the LaB6 emitters, the current density is between 10 to the 3 and 10 to the 6 Amps per centimeter. Thus, the field emission gun is hundreds of times brighter than a thermionic emission source. Furthermore, since the electrons are field generated rather than thermally generated, the tip remains at room temperature. Tips are usually made from tungsten etched in the <111> plane to generate the lowest work function. Because a native oxide will quickly form on the tip even at moderate vacuum levels (10 μPa), a high vacuum system (10 nPa) is needed. To keep the tip diameter sufficiently small, the cathode warmed to 800-1000 °C or rapidly heated to approximately 2000 °C for a few seconds to blow off material.

This table below summarizes the basic capabilities of the four basic configurations, where we break the cold field emission and Schottky field emission systems into their own separate groups.The highest performers are the field emission systems, which include cold cathode and Schottky. The high brightness and sharp tip leads to high resolution and longer source lifetimes. Notice that both tungsten and LaB6 have lower brightness, lower resolution, and reduced source lifetimes. However, the lower vacuum requirements can facilitate more rapid sample exchange, especially when venting the column is necessary. For more information on the Cold Cathode and Schottky field emission systems, please see the Technical Tidbit on this topic elsewhere in this newsletter.Higher tunnel magneto resistance improved the read speeds to on the order of 10 nsec. Unfortunately, the current needed for MRAM devices increases as the dimensions decrease, limiting the usefulness of this type of device.

April 1, 2011

Future Memory Technologies – Part 4
By Christopher Henderson

This month we conclude our series of articles on the future of memory. The final future memory technology we will cover is based on spintronics or spin transport electronics. Another common term for this technology is magnetoelectronics. These devices are also sometimes referred to as MRAM, or Magnetoresistive Random Access Memory. MRAM has been in development since the 1990s, and several companies have introduced production devices. The basic memory cell is a dual stripe of anisotropic magnetoresistive (AMR) layers separated by a nonmagnetic spacer. AMR materials were also used in the read head of magnetic recording hard disk drives. AMR is a change in the resistance of ferromagnetic conductors depending on the angle between the magnetization and the current. The magnitude of this effect is only about 2% for the most common magneto-striction-free NiFe or NiFeCo alloys suitable for device applications. The simplest form of GMR or Giant Magnetoresistive films consist of two magnetic layers separated by a Cu spacer, and had a magnetoresistance ratio of 6% initially and later more than 10% with improvements. The image below shows a drawing of a typical MRAM cell.

Figure 1. Drawing depicting a Magnetoresistive RAM cell or MRAM cell

Higher tunnel magneto resistance improved the read speeds to on the order of 10 nsec. Unfortunately, the current needed for MRAM devices increases as the dimensions decrease, limiting the usefulness of this type of device.

Researchers working to address problems with MRAM technology discovered that it is possible to use an alternate quantum mechanical property in the magnetic tunnel junction by changing the magnetic orientation of the thin magnetic layer. Basically, charge carriers such as electrons have a quantum unit of angular momentum or spin. An electrical current is generally unpolarized, consisting of 50% spin-up and 50% spin-down electrons whereas a spin-polarized current contains more electrons with a particular spin state. Researchers have demonstrated that it is possible to transfer spin angular momentum to a small magnetic element through a spin-polarized current. Spin-transfer torque RAM or STT-RAM has the advantages of lower power consumption and better scalability compared to conventional MRAM. In particular, the write current scales down with size, whereas MRAM write current scales up as the size of the cell decreases. Today, Sony and Hitachi are working as a team to develop this technology and introduce commercial parts in the near future.

Figure 2. Cross-section of a Spin Transfer Torque (STT) RAM cell.

The graph below shows the scaling of current for both MRAM and Spin Transfer Torque RAM. Notice that the current scales down as the feature sizes decrease for STT-RAM. The opposite is true with regular MRAM.

Figure 3. Current vs. cell width for MRAM and STT-RAM devices.

In conclusion, there are a number of potential memory technologies that may take the place of flash memory in the future. This table shows several of the leading candidates: ferroelectric memory, magnetoresistive RAM, phase-change RAM, and spin transfer torque RAM. Each device has its advantages and disadvantages. Current generation flash memory is increasingly limited by its cycle endurance. High voltage is required to write and erase flash memory, and the write power is very high. Ferroelectric memory solves the "high voltage" and "write power" issue, but falls short on endurance. MRAM has a high endurance level, but the write power becomes worse as the devices scale down. Phase-change memory has low write power, but is somewhat limited in endurance. STT-RAM shows the most promise, but its development is still in its infancy, and the problems with write current have not been completely solved. Magnetic nanopillars is in its infancy, and is not shown on this table. Researchers and device manufacturers are likely to pursue these technologies for some time to determine which one will ultimately replace Flash as the reigning non-volatile memory.

Table 1. Comparison of Memory Technologies.

March 1, 2011

Future Memory Technologies – Part 3
By Christopher Henderson

Figure 1. Basic concept behind magnetic nanopillar memory operation.

Researchers are also investigating other types of memories for the future. As we approach the limitations imposed by physics on charge- based memories, new architectures will be needed to scale down further. One potential memory technology that is generating some interest is magnetic nanopillars. Another commonly used acronym for nanopillar technology is RAMA. It stands for reconfigurable array of magnetic automata. Researchers have already demonstrated that a random array of up and down polarized ferromagnetic pillars (CoFe2O4) embedded in a ferroelectric or multiferroic matrix (e.g., BiFeO3) can have their magnetizations rotated from being perpendicular to the pillar (and the film) surface to being in-the-plane of the film with the application of a modest electric field.

Figure 2. Construction of magnetic nanopillar devices.

This technique is being explored to create magnetic nanopillar devices. Wires are formed on a substrate using nanoimprint lithography, electron beam lithography, or other lithographic techniques. The ferromagnetic pillars are constructed through lithographic methods or polymeric self-assembly.

The ferroelectric material resides in columns within the piezoelectric material or matrix to form potential connections between two conducting planes. The lower part of the ferromagnetic material forms the nanopillar, while the top portion is the colossal magnetocapacitive material, such as LaPrCaMnO3, LaSrMnO3 or other manganite. This material is called a colossal magnetocapacitive (CMC) material, because such a capacitor built of this compound can exhibit large changes in capacitance with changes in magnetic field. Patterning metal, etching the material where it is not needed, and depositing insulating material between the conductors form the top connections. Researchers at the University of Virginia and others have described this type of approach.

Table 1. Comparison of Magnetic Nanopillar or RAMA with standard CMOS SRAM technology.

Notice that RAMA, or nanopillar technology has some potentially significant advantages over standard memory technology. Notice that the nanopillar technology can be made through polymeric self- assembly, potentially reducing the cost of the device. The cell size can be smaller, allowing for greater bit density. The switching energies are much lower than for standard memory, but the switching speeds are also much lower. RAMA can also be made to be compatible with existing CMOS processing.

February 1, 2011

Future Memory Technologies – Part 2
By Christopher Henderson

Another contender as a future non-volatile memory technology is Resistive Random Access Memory, sometimes shortened to RRAM or ReRAM. A prototype RRAM chip is shown in Figure 1. Several major manufacturers are working on RRAM, including: Samsung, Micron, Macronix, and Elpida Memories. The technology is somewhat similar to Conductive Bridging RAM and Phase Change Memory, which we discussed in the previous issue. IMEC in Belgium has also done extensive research into this technology.

Figure 1. 128 Kbit RRAM array from a collaboration between AIST, Sharp, ULVAC, and Kanazawa University.

Figure 2. Cross-section of an RRAM cell. The switch is located in the backend of the process.

The basic concept is that one can create a conducting path through a dielectric layer by applying a high voltage (see Figure 2). The conducting path, or filament can be reset, restoring the high resistance path and reformed to create a low resistance path at will. This filament path may actually be multiple paths, according to researchers. There are different types of materials that can exhibit this behavior. They include perovskites, chalcogenides, and transition metal oxides. Some of the leading transition metal oxides include nickel oxide, titanium oxide, tungsten oxide, hafnium oxide, and heterostructures such as aluminum oxide/titanium oxide. Ironically, even silicon dioxide can be used for this application. The failure mechanism engineers try to avoid in standard CMOS, time-dependent dielectric breakdown, is the mechanism by which the programming occurs.

Figure 3. Forming, reset and set currents for a Resistive RAM test structure (area = 2x10-5 cm2, HfO2 thickness of 5nm and TixNy electrodes. The researchers used a current compliance of 10-4 Amps

RRAM has the potential to become the front runner for future memory technologies. RRAM can operate much faster than Phase Change Memory. The switching time can be on the order of 10ns. Compared to MRAM, RRAM has a much smaller cell size. The cell size is less than 8F2, where F is the smallest feature size. It can also function at lower operating voltages than standard flash memories. RRAM also has the potential to scale down below 30nm. While standard flash memory is now below 30nm, the cell size is larger, so RRAM can still accommodate more cells in the same silicon area. Researchers believe that the mechanism might involve oxygen motion, which might allow for scaling down to as low as 2nm. The filament dimensions during the forming process are also key factors to a stable, reliable device(1)

(1) G. Bersuker, et. al., "Diode-less Nano-scale ZrOx/HfOx RRAM Device with Excellent Switching Uniformity and Reliability for High-density Cross-point Memory Applications," Proc. Int. Elec. Dev

January 1, 2011

Future Memories – Part 1: Phase Change Memory
By Christopher Henderson

This article is the first in a series of articles on new memory technology. As we quick approach the limits of scaling in traditional DRAM and Flash memories, new memory technologies will be needed if we wish to continue creating smaller, more feature-rich electronics. In this first segment, we will discuss Phase Change Memory. In future issues we will also cover resistive RAM, several quantum magnetic devices, carbon nanotubes, and molecular memories. One of the big problems with scaling today's flash and DRAM memories further is the limit on charge storage. Cell sizes are approaching the point where the amount of charge stored in a single DRAM or Flash memory cell is down into the thousands of electrons. At this level, leakage, process variation, variation in the application, retention times, and a host of other variables become problematic. These problems will likely limit future scaling below 20nm. There are several technologies that have the potential to permit scaling beyond this point. We will discuss one of the leading ones, Phase Change Memory, in this issue. Phase Change Memory is one of the most developed replacement technologies.

There are actually production devices on the market from companies like Micron (formerly Numonyx), and Macronix. Phase-change memory is a type of non-volatile computer memory. It is also known as PCM, PRAM, PCRAM, Ovonic Unified Memory, and C-RAM. Phase change memory uses the unique behavior of a chalcogenide glass. With the application of heat produced by the passage on an electric current, this material can be "switched" between two states, crystalline and amorphous. Table 1 shows some of the properties associated with the chacogenide structure. Recent versions can achieve two additional distinct states, effectively doubling its storage capacity. Phase change RAM is one of a number of new memory technologies competing in the non-volatile role with the almost universal Flash memory. Examples of such phase change materials are GeSbTe and AgInSbTe. Micron in particular uses Ge2Sb2Te5 for its phase change memory devices.

Figure 1 shows the cross section cutaway of a phase change memory cell. In this technology developed by IBM and Macronix, the cell uses a common source line for the transistors associated with the two cells. The word line forms the gate connection for the transistor, and the drain connects to the chalcogenide material. The bit line runs perpendicular above the cell, and is used to program the cell by changing the state of the chalogenide material from polycrystalline to amorphous, or vice versa. The smaller the chalogenide bridge is, the less current required to program the cell.

Phase change memory requires high programming current densities, which is a distinct drawback. To program the cell, current densities of greater than 107 A/cm! (compared to 105-106 A/cm! for a typical flash memory cell) are required. This has led to active regions which are much smaller than the driving transistor area. The discrepancy has forced the manufacturers to package the heater and sometimes the phase-change material itself in sublithographic dimensions. This results in additional expensive processing, which is a cost disadvantage compared to Flash.

Table 1 – Phase Change Memory (PCM) Properties

The contact between the hot phase-change region and the adjacent dielectric is another fundamental concern. The dielectric may begin to leak current at higher temperature, or may lose adhesion when expanding at a different rate from the phase-change material. Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended phase-change. This stems primarily from the fact that phase-change is a thermally driven process rather than an electronic process. The thermal conditions that allow for fast crystallization should not be too similar to standby conditions, e.g. room temperature. Otherwise data retention cannot be sustained. With the proper activation energy for crystallization it is possible to have fast crystallization at programming conditions while having very slow crystallization at normal conditions. Probably the biggest challenge for phase change memory is its long-term resistance and threshold voltage drift. The resistance of the amorphous state slowly increases according to a power law, which goes by approximately t0.07 (see Figure 2). This severely limits the ability for multilevel operation (a lower intermediate state would be confused with a higher intermediate state at a later time) and could also jeopardize standard two-state operation if the threshold voltage increases beyond the design value.

Figure 1 – Cross section cutaway of a Phase Change Memory Cell. 2 cells are shown in the drawing at the left.

Figure 2 - Graph showing resistance increase as a function of time in a Phase Change Memory cell.

Technical Tidbit

March 15, 2015

Stress Voiding Prerequisites

There are three prerequisites for stress voiding: a driving force, a nucleation point—or a mechanism to initiate the growth, and a means to grow. The driving force is provided by the tensile mechanical stress that is built into the interconnect after it is deposited, cooled, and confined by the dielectrics that surround it and prevent it from relaxing. A second method that introduces stress into the system is the intermetallic reaction that can occur in aluminum systems with titanium-based shunt layers. We’ll discuss both of these in more detail in a few slides. The way to start is normally provided by some type of defect. This could be as simple as a small cavity on the side of an interconnect. The means to grow is provided by nature in the form of diffusion, or mass transport away from the void along the path of least resistance, normally a grain boundary.

Let’s discuss the two sources of mechanical stress in more detail. The first stress mechanism is brought on by the mismatch in coefficients of thermal expansion between the interconnect and the dielectrics that surround it. Aluminum has a much higher coefficient of thermal expansion than silicon dioxide. As the interconnect and surrounding dielectrics cool after the deposition process, a stress is induced in the line. The higher the processing temperature, the more stress is placed on the interconnect at normal temperatures.

The second stress mechanism is brought on by the intermetallic reaction between aluminum and titanium. Sometimes, circuit manufacturers will react—or sinter—the aluminum with the titanium shunt layer to prevent it from delaminating and to insure a low resistance connection between the two layers. The resulting intermetallic product takes up less room than the two metals separately. If this system is again confined by the dielectrics, this places a stress in the system.

February 16, 2015

TSV Stresses

The stresses generated by the TSV not only affect the interconnect ends, but they also affect the stress in the silicon. In fact, sufficient stress is generated to result in transistor mobility variations. In today’s nanometer-scale technologies, a slight variation in mobility in some transistor can result in the design not working. Researchers at CEA-LETI in France have modeled the effects of stress. Here are two examples of modeling work showing how the TSVs affect stress during temperature cycling, and the molding process.

In these examples, the silicon die with TSVs is stacked on top of a MEMS chip. Notice the high stress values at the corner, but even these are significantly less than the stress values associated with the maximum point in the vicinity of the TSVs. This requires coordination between the silicon chip designers and the packaging engineers – an activity we normally refer to as chip-package co-design. The result might mean the creation of Keep Out Zones (KOZs) for sensitive transistors.

January 18, 2015

Die Attach Film

A die attach film or DAF, can be an alternative to using epoxy tubes. Die attach film is a product that combines dicing tape and die attach into one single sheet. This is a high volume manufacturing process, and die attach films can be used where one does or does not need an electrically conductive path between the die substrate and the leadframe. Die attach film can also provide a more uniform bond line, create a uniform fillet, and avoid die tilt problems. Die attach film typically comes in rolls like we picture here, where the DAF is the same size as the wafer. Accordingly, these rolls can be for 150, 200, or 300 millimeter wafers.
A die attach film can provide a method to facilitate sawing and mounting of small dice. One of the big challenges with small dice and die attach paste is making sure the device is level during the mount process on the leadframe. These die attach films are designed to work with a variety of die sizes (from 0.2mm to 10mm on a side), with thin dice (down to 50um), with wafer metallization schemes (including no metallization, TiNiAg, and Au) and leadframe metallization (Cu, Ag, Au, NiPdAu). Die attach films are thin, so there is less risk of the die shifting during the mount and cure operations. Die attach films are shelf-stable, so they can be shipped and stored under normal temperature conditions. Die attach films eliminate the formation of a die attach fillet. Elimination of the die attach fillet saves room in the package design, which can lead to lower Au wire costs (less wire used for bonding), lower mold compound costs (smaller package), and lower leadframe costs (smaller leadframe). This can also be useful when placing die close together in a small package. One drawback to a die attach film is that it can lead to higher stress conditions in some package material systems.

The process for using a die attach film is similar to standard wafer dicing tape. First, one spreads out the die attach film over the ring frame and then cuts the die attach film to fit the ring frame. One then mounts the silicon wafer to the die attach film. Next, one proceeds with the dicing operation. After the dicing operation, one applies ultraviolet radiation to the backside of the film to reduce the tack of the film. Finally, one can then use a pick and place tool to lift the die (and the die attach film under the die) from the tape and place it on the leadframe for mounting and curing.

December 21, 2014

Vertical Probe Cards

An increasingly common type of probe card is the vertical probe card. The image on the left shows an octal (8) site vertical probe card from Form Factor. The probes pass through two offset plates, which create a bend in the probes. A reduction in the amount of bend in the probes lowers the probes and generates the pressure on the pad required to make positive contact. This approach or technology is sometimes known as buckling beams. We show examples of the probe marks on the pads in the image on the right. The probe mark left by the vertical probe is typically smaller than that left by a cantilevered probe. This type of probing will generate fewer particles, and can facilitate probing an array of pads, since the probes do not take up as much lateral area as cantilevered probe tips.

November 16, 2014

Outlier Screening

An outlier is a product that meets the manufacturer specifications and user requirements but exhibits anomalous characteristics with respect to a normal population.

The blue region corresponds to the main portion of the population, while the red data corresponds to the outliers. Outliers can be a problem because some is different with respect to these devices, causing them to fall outside the normal distribution. There is significant evidence from failure and yield analysis work that outliers can then degrade and drift outside the limits set by the product engineers in the product specification. Therefore, it makes sense to eliminate these parts before shipping them. One can use different variables to identify outliers: parametric values associated with transistors, bin data associated with failure modes, continuity/shorts data and overall wafer yield values. Outlier programs can be implemented at parametric test, wafer sort, and at final test. JEDEC Standard JESD50B-01 defines how to run an outlier program, but it does not prescribe how to do the statistical analysis. Most companies will use one or a combination of the following algorithms: the Tukey algorithm, the Cpkn algorithm or the 3 Sigma algorithm to set statistical limits to identify outliers (represented by the dashed red lines in the figure). There are other criteria applied to the identification and disposition of these parts. For more details, see the Outlier Section in the Test or Reliability workspaces on the Online Training Website.

October, 19, 2014

Process Capability Index

Process Capability Index, or Cpk is an important topic for Product and Manufacturing Engineers to know. Cpk is an index in the form of a simple number which measures how close a process in running to its specification limits relatively to the natural variability of the process. The Cpk index is part of a series of indices that measure how much natural variation a process experiences relative to its specification limits and permits the engineer to compare different processes to one another with respect to their overall control. The larger the index number, the less like any particular data point will be outside the specification limits. However, a large index is not necessarily a good thing, so engineers may tighten the limits if there is a large Cpk. If Cpk is too large, one never sees an indication that prompts action to fix or optimize the process.

This table describes the process capability indices and the equations to calculate them. Although there are a number of indices, Cpk is the most popular. Process capability indices assume that one is dealing with normally distributed data, and that may not always be the case. It’s important to remember though that some data might have an upper bound, but no lower bound, or vice-versa. An example of this might be quiescent power supply current (IDDQ), or maximum frequency (Fmax). IDDQ typically has an upper bound, but no lower bound, whereas Fmax typically has a lower bound, but no upper bound.

Let’s use a car and a garage as an analogy. The garage will define the specification limits, and the car will define the output of the process. We show four scenarios with cars and garages. If my car is only a little bit smaller than the garage, then I need to park it right in the middle of the garage (center of the specification) if you want to get all of the car in the garage. This is similar to a Cpk of 1. It is a marginal outcome. If my car is wider than the garage, it does not matter how I try to center it, because it will not fit. This is similar to a Cpk of less than 1. It is an unacceptable outcome. If my car is a lot smaller than the garage, it doesn't matter if I park it exactly in the middle, because it will fit and have plenty of room on either side. This is similar to a Cpk of greater than 1. If I can always park my smaller car in the center and with little variation, then this is equivalent to the highest Cpk value, or a value that is much greater than 1. Cpk describes the relationship between the size of the car, the size of the garage and how far away from the middle of the garage I parked the car.

So what is an acceptable value? Clearly, values that are below 1 will be unacceptable, and a value of 1 will be marginal, but what about larger values?

In general in semiconductor manufacturing, we would like to see values equal to or greater than 2.00. This would constitute excellent process capability. A value of 1.33 would be acceptable, and a value of 1.67 would be good. These numbers will obviously vary depending on the process and the type of testing performed to generate the data. Some procedures like trim tests will have lower Cpks, but that is not necessarily a problem, as the purpose of trimming is to improve Cpk.

September, 21, 2014

Leakage in Reverse Biased Junctions

Leakage in reverse biased junctions is an important concept to understand. It plays a key role in the types of applications and use conditions for which we can use silicon circuits. Junction leakage is primarily the result of thermally generated carriers in the depletion region. As carriers are generated, they will be subject to the electric fields present in the depletion region. This will cause electrons to travel toward the N-doped material, since it is positively biased, and holes to travel toward the P-doped material, since it is negatively biased. Figure 1 shows the carrier generation process, and Figure 2 shows the carrier movement after generation. Since leakage current is thermally generated it is exponential with temperature. Leakage currents will double about every eight or ten degrees Celsius in silicon. Silicon “goes intrinsic” at temperatures just above 400C, meaning that the thermally generated carriers actually outnumber doping-generated carriers. Germanium exhibits weaker bonding than silicon and therefore leaks significantly more. For most circuit applications silicon IC’s are good to about 150C whereas germanium would only be good to maybe 100C.

Not only can heat be a source of carriers, but other mechanisms can generate these carriers. For example, light can do this. If one places an exposed reverse-biased pn junction under a probe station with the lights on, one can see the increase in leakage in the junction. The energetic photons from the light inject enough energy to create some number of electron-hole pairs. Another mechanism that can produce this effect is ionizing radiation.

The junction leakage is basically independent of the reverse bias. In other words, it does not increase as the electric field increases, but rather remains relatively constant. Temperature is the main effect.

August 24, 2014

Visualizing Diffusion

Most of us usually learn about diffusion in college in terms of their mathematical equations. However, visualizing diffusion can make it much easier to understand. This series of images can help us visualize the concept. Let’s assume we have a hypothetical situation where we have a number of charge carriers in a box like we show here.

These carriers will move around within the box, and the speed of their movement will be governed by the temperature of the system. The lower the temperature, the slower the carriers move; the higher the temperature, the faster the carriers move. Notice that we have a lot of carriers on the left, and no carriers on the right.

Now, let’s remove the wall. Since the carriers move randomly, about half are moving to the left and half are moving to the right at any given point in time. Those near the boundary can now move across the boundary. Because the barrier is now missing, there is a net movement to the right, because those right on the boundary have a 50% chance of moving to the right, and a 50% chance of moving back to the left. Fick’s Laws are the equations that govern this motion.

In general then, we have this random motion that results in a definite and predictable motion of the entire population of the carriers, and we call this Gaussian or Fickian diffusion. Like the movement of carriers, diffusion slows down with temperature, and with state changes from liquid to solid, but it still occurs, even at very low temperatures.

Not only does this occur in semiconductor materials, but it is also associated with other mechanisms, like intermetallic growth. For instance, Kirkendall voiding with intermetallic growth as an example of this, since diffusion of gold into aluminum occurs more quickly than diffusion of aluminum into gold.

July 27, 2014

Al-Si Metal Systems

Some companies use different percentages of silicon in their aluminum-silicon (Al-Si) metallization systems. This phase diagram helps to illustrate why one might choose different percentages.

If we look at the phase diagram, we see 100% Al on the left and 100% Si on the right. The melting temperature for Al is 660°C, the melting temperature for Si is 1414°C, and the eutectic temperature (at 11.3% Si) is 577°C. We are interested in how much Si we can incorporate into the Al in solid solution – the region at the lower left. We have expanded that region in the white inset graph. Notice that at Al-0.5%Si, the solid solution temperature can be as low as 500°C whereas with Al-1%Si, the solid solution temperature can only be as low as 550°C. This means that if we want Al-1%Si, we’ll need to do the deposition at 550°C or higher, whereas with Al-0.5%Si, we can do the deposition as low as 500°C. A lower deposition temperature can be beneficial from a thermal budget standpoint, creating less damage. On the other hand, a higher percentage of Si in the Al will better prevent Si nodules. This is the basic tradeoff process engineers face with Al-Si metal systems.

June 29, 2014

Composition Resistors

The construction of a composition resistor is straightforward to understand. One uses machinery to hot press a cylinder of graphite and organic binders. One embeds leads in both ends of the graphite, the resistive material. The component is then covered in a thermoset polymer package and cured to create a solid cylinder-shaped component. These devices are not precise, and engineers typically use them in circuits where lower precision is acceptable. A composition resistor typically is only accurate to about 10% of its intended resistance value.

The image to the right shows an example of a typical composition resistor. The colored bands indicate the resistance value of the component. For more information on how to interpret the color bands, the reader show access IEC Standard 60062. There is also information on this topic at a number of websites, including Wikipedia. Most components contain four bands to list the first and second significant digits, the multiplier, and the tolerance. This component is a military component and has 5 bands; the fifth band indicates the failure rate. This particular component is a 1 megaohm resistor (red – which represents a “one” for the first significant bit, brown – which represents a “zero” for the second significant bit, blue – which represents the “six” for the 10 to the 6 multiplier, and gold – which represents a 5% tolerance. The image at the lower right shows a cross-sectional view. We can see the hot-pressed carbon element, the lead to element interface, and the thermoset compound encasing the element and the ends of the leads.

Some typical failure modes for composition resistors include resistance increase due to moisture, electrical overstress damage, and mechanical damage. Moisture can lead to an increase in resistance. Moisture will penetrate through the thermoset, much like it does with a plastic encapsulated microcircuit. The moisture penetrates into the carbon element, causing swelling of the binders, leading to a change in the volume percentage of the carbon and a higher resistance. Baking most composition resistors will return the resistance back to normal. One can improve the humidity resistance through the use of coatings on the resistor component, or a conformal coating on the board. Electrical overstress is a common failure mode, and is often accompanied by signs of charring, cracking or burning at the exterior. Finally, mechanical damage can manifest itself as damage to the body of the resistor (a cracked package) or cracking at the interface between the leads and the resistive element.

May 30, 2014

RESURF Technology

RESURF (also spelled without capital letters as resurf) stands for reduced surface field. This is a concept that takes advantage of the behavior of the depletion region in a p/n junction when one of the materials is confined. The following two figures show the principle behind RESURF. The basic device structure is shown here. It consists of a high voltage diode on a lightly doped p- substrate with a slightly higher-doped epitaxial n- layer on it, which is laterally bounded by a p+ isolation diffusion, shown on the left. The diode therefore consists of two parts: a lateral diode with a vertical n-/p+ boundary and possible lateral breakdown, and a vertical diode with a horizontal n-/p- boundary and possible vertical breakdown. For a thick epitaxial layer (~50μm) the breakdown voltage is ~500V and the maximum field is at the surface at the n-/p+ junction. The light magenta color denotes the depletion region in both images. Notice that the lateral electrical field EL is high near the n-/p+ junction.

For a much thinner epitaxial layer (~15μm) the depletion layer of the vertical n-/p- junction influences the lateral depletion layer, and reducing the surface field. Since the depletion region consumes the entire n- epi region, the electrical field behavior is much different. This is a two-dimensional effect. At a higher voltage (~1200V) the field at the surface has 2 peaks, one originating from the n-/p+ junction and another just below the surface at the curvature of the n+/n- junction, with a moderate field in between. Notice that the lateral electrical E sub L is much smaller near the n-/p+ junction. This not only supports higher breakdown voltages in the structure, but reduces hot carrier damage in the oxide near the n-/p+ junction. If the lateral distance is sufficient, breakdown only occurs vertically in the semiconductor body under the n+ region. Many power semiconductor manufacturers use this technique to create higher performance devices and improve the reliability as well. However, there are some negative effects, like the emergence of the Kirk effect at the n-/n+ junction. RESURF also impacts RDS(ON), but this can in many instances be optimized by adjusting the layout, technology dimensions, and the doping levels. RESURF techniques can be used for discrete transistors, like power npn or pnp transistors, vertical DMOS (VDMOS) devices and lateral DMOS (LDMOS) devices.

April 27, 2014

Packing and Shipping Labels

After initial packing, the reels, tubes, and trays are usually then packed into boxes for shipping. Most large semiconductor manufacturers use distribution centers located in or near major worldwide shipping hubs. Most components are also small enough that they can be shipped by air via UPS, FedEx, DHL, or other couriers. One concern with shipping components is that components are generally static sensitive, and the shipping process does not allow for static control. In order to protect the components, engineers will use static protective bags, tubes and reels. Furthermore, they use labels to indicate that the components being transported are static sensitive. The semiconductor industry uses labels like the ones we show on the right to indicate static sensitivity. The military requires labels, and JEDEC-compliancy requires the labels as well. One must put labels on the unit pack and the intermediate and exterior containers.

Components also need to be labeled as to their moisture sensitivity. The moisture that is being absorbed by the device is inherent during the assembly and molding process and this moisture trapped within the device may cause the unit to crack, known as the popcorn effect, during IR reflow, vapor phase reflow, or similar processes at board mounting operation due to the high amount of heat that is being applied. The bake step we mentioned removes this trapped moisture inside the package at a slower pace without causing any package cracking or solderability concerns. The units can then be dry packed afterwards to ensure no moisture absorption will take place until the devices are ready to be mounted to the boards by our customers. Operators then list the MSL sensitivity on the labels on the exterior of the box and dry-ship bags.

March 23, 2014

Lithography Alignment

Alignment during lithography is a critical activity. Any type of misalignment can lead to non-functional circuits. In order to print the features on the circuit, the mask must be aligned to the wafer features. How do engineers do this? They use alignment marks printed on the wafer from the previous mask step or steps. The image below (Fig. 1) shows an example of alignment marks. Quite often, alignment marks consist of box-like structures with a cross internal to the box. The criticality of the alignment can be defined by the width of the cross in the box. A narrow cross indicates a more critical or closely aligned step. There are many types of alignment errors. The list includes mask errors, stage errors, and wafer chucking errors. These alignment errors are straightforward to understand and can usually be corrected through proper calibration and procedures. Another type of alignment error can occur from lens distortion or magnification. This type of error can be more severe, requiring one to re-polish or even replace the lens. Some alignment problems result from wafer processing. Thermal processes and the use of stressed films can produce a bow in the wafer, which leads to alignment issues. An asymmetrical resist coating can lead to depth of focus issues or refraction problems that impair alignment. Chemical mechanical polishing can lead to a non-flat wafer surface which affects alignment. Overlay metrology errors can also impact alignment.

Here are some examples of overlay errors (see Fig. 2). The blue lines represent the ideal grid and the red lines show the actual chip positions. Here we show eight different types.

Examples of overlay errors: (a) global offset, (b) global scaling, (c) global rotation, (d) orthogonality, (e) field magnification, (f) field rotation, (g) distortion, (h) trapezoid.

February 23, 2014

No Technical Tidbit section this month.

January 26, 2014

Low Emission Packaging Materials

An increasing problem with modern ICs is their susceptibility to soft errors. A soft error can be caused by an alpha particle striking a sensitive region on a circuit, like a memory cell or register, creating a temporary logical error in the circuit. Alpha particles can come from a variety of sources, but those sources need to be in close proximity to the active transistors in order for the alpha particles to create the charge necessary to cause an error. A leading cause of alpha particles that cause this problem is contamination in the solder bumps and plating materials used to connect the die to the package leadframe or substrate. In order to minimize this problem, some manufacturers have turned to “Low alpha” or “Low emission” materials. Basically, a Low alpha material is a material that has undergone more extensive purification to reduce the contamination level of radioactive elements. These images show examples of some of the materials for which engineers create low emission variants.

Figure 1. Low alpha tin spheres (left), and low alpha tin-copper (right)

Figure 2. Low alpha tin oxide powder (left), and low alpha tin pellets (right)

Figure 3. Low alpha lead - 4N purity (left), and low alpha lead pellets (right)

Figure 4. Low alpha lead oxide powder (left), and low alpha anodes (right)

Figure 5. Low alpha tin-silver-copper (images courtesy CSC Pure Technologies)

While not all applications require this care with materials, systems that must operate without errors, or systems with large amounts of memory, can require these materials to avoid potential problems.

December 22, 2013

IDDQ Behavior and the Curve Tracer

Quiescent Power Supply Current (IDDQ) is a powerful way to examine a component during a failure analysis effort. Many types of defects can be identified from the IDDQ signature. We won’t go into why this is so here, as there is more information on this topic on our Online Training site. However, we will discuss the nature of the IDDQ measurement and what it tells us.
First, let’s discuss how to make a Quiescent Power Supply Current (IDDQ) measurement on a bench setup. To perform this test, one needs a curve tracer or a parameter analyzer, a switchbox capable of connecting to the curve tracer and the device, and the device to be tested. The analyst should then place the IC in a non-contention state. A non-contention state is one where there are no transistor outputs trying to drive a logical high and a low at the same time on the same node. In order to remove the contention, it may be necessary to clock the IC or input a few vectors to the appropriate inputs. The analyst should tie all of the inputs to either VDD or VSS, float all of the outputs, and sweep the voltage on the VDD side from the maximum rated supply voltage down to zero. This will yield a curve similar to the curve shown in the lower left portion of this slide.

Figure 1. Basic setup for IDDQ on a curve tracer.

Figure 2 shows some actual examples of IDD-VDD curves. These are all taken from microprocessor analysis work done several years ago. The microprocessors are 0.5µm CMOS circuits with approximately 800,000 transistors. The curve on the upper left has an obvious parabolic shape to it. Subsequent failure analysis localized the problem to a gate oxide short in an n-channel transistor within the random logic. The curve on the upper right shows a linear shape. In this case, the defect was localized to a high resistance short between VDD and VSS. In the example in the lower left, the IDD-VDD curve exhibits an exponential characteristic. The current is well within the specified limits at 3.3 volts and 5.0 volts, but it increases rapidly at about 5.5 volts, somewhat sooner than a defect-free circuit. This leakage is due to a soft pn junction, and possibly attributable to electrostatic discharge damage. The IDD-VDD curve on the lower right has an erratic shape to it. We created the IDD-VDD curve by sweeping from the supply voltage down to zero. Notice that the current starts at a low value, then jumps high. It then meanders erratically downward until about 1 volt, where it then drops to a low value. An erratic, time-varying current is indicative of an open circuit defect.

Figure 2. IDD-VDD curves associated with various defects. Gate oxide short (upper left), VDD-VSS bridging short (upper right), ESD damage causing soft breakdown (lower left), and open vias (lower right).

November 24, 2013

I2C Interface

This month’s technical tidbit describes the Inter-Integrated Circuit Interface, or I2C interface. It is a two-wire interface that is gaining increased acceptance as an analog design for test technique to test complex analog circuits.
The I2C interface was developed by Philips Electronics in the early 1980s as a method to attach low speed peripherals to a personal computer. Although this interface has long since disappeared for personal computer devices in favor of the Universal Serial Bus, it still is used for testing purposes on integrated circuits. Although the original specification for I2C called for a 100kHz operating frequency, newer versions of the I2C standard run at frequencies as high as 5MHz.
This drawing shows a block diagram of the I2C interface. There are two pins that interface to the outside world, SDA, the data line, and SCL, the clock line. This extremely low pin count interface is popular for circuits with limited pins, as this interface can be implemented with just two pins. Basically, one microcontroller acts as a master device, and the rest of the devices then operate as slaves to the master. The I2C bus uses pull-up resistors to the power supply, so the combination of those resistors and the capacitance of the SDA and SCL lines limit the frequency of operation.

Fig. 1. I2C Bus block diagram

There are four operating modes for the I2C interface: master transmit, master receive, slave transmit, and slave receive. The most common data and address format is 7-bits, but some versions run with 10-bits. Data transfer is initiated with the Start bit when SDA is pulled low while SCL stays high. Then, SDA sets the transferred bit while SCL is low (blue) and the data is sampled (received) when SCL rises (green). When the transfer is complete, a Stop bit is sent by releasing the data line to allow it to be pulled up while SCL is constantly high. In order to avoid false marker detection, the level on SDA is changed on the falling edge and is captured on the rising edge of SCL. The address and data arrive with the most significant bit first.

Fig. 2. Bus Protocol for I2C Interface.

An example of a chip that uses this interface is Linear Technology’s LTC2309, an 8-channel, 12-bit Successive Approximation Register (SAR) Digital-to-Analog Converter (DAC). The data input to the DAC uses the I2C interface.

Fig. 3. Linear Technology’s LTC2309 uses the I2C bus as an interface to the DAC.

October 20, 2013

Parallel Test Efficiency

One method for reducing the cost of test is to test components in parallel on the same test system. Test engineers commonly use this approach on devices with low pin counts. Many analog and mixed-signal devices fall into this category. Ideally, one should be able to achieve a factor N speedup, where N is the number of devices tested in parallel. Sometimes N is referred to as the number of test sites, or simply number of sites. In reality, one cannot achieve this ideal increase in test efficiency. Factors like program loads and setups for parallel testing cannot be shrunk, so one cannot achieve 100% efficiency in parallel test. Therefore, engineers use a concept called Parallel Test Efficiency, or PTE, to describe the increase from multi-site testing.

The equation for Parallel Testing efficiency is:

where:
x is the parallel test efficiency
N is the number of sites
Tm is the multi-site test time
Ts is the single site test time

We can write this in a different form if we’re interested to determine the multi-site test time.

, where is the parallel component and is the serial component.

Let’s work an example then. Let’s assume that we have a test configuration for a single site test and a four-site test. Let’s assume the test times are 0.65 seconds for the single site and 0.95 seconds for the four-site test. The parallel test efficiency would then be:

February 22, 2011

Dice Before Grinding

Usually, wafers are ground down before the sawing operation. However, some organizations have been exploring a process where the sawing operations occur first, followed by the backgrinding operation. This is sometimes referred to as "Dice Before Grinding", or DBG. The conventional grind before sawing is shown in the upper row. Three variations of the DBG approach are shown in the lower rows. DBG can be done with or without Chemical Mechanical Polish, or CMP. CMP can be useful when a higher quality interface is needed between dice. DGB can also be accomplished using standard wafer saw processes, or with reactive ion etching.

One concern with thin dice is how to handle them. The dice are especially prone to damage during pick and place operations. The key is to initiate the peeling process from the backing tape without damaging the dice. This diagram shows an approach to doing just that. This process involves raising and then lowering the ejector assembly. By raising it, one can initiate the peeling process at the edge of the die. By then lowering the ejector assembly, one can achieve a controlled peeling process in which the backing tape peels away from the die, but the die is held in position by the ejector pins.

January 15, 2011

Backgrinding

Wafer backgrinding is a common technique to thin dice for packaging in thin profile applications. Understanding the behavior of silicon during backgrinding is important to achieve success. Generally speaking, silicon is a brittle material, breaking with sharp edges and cracks (similar to glass). However, Si-II (pronounced "silicon-two") has lower yield strength, which is relatively easily deformed with better elongation. This is similar to most metals. For reference, Si-II is a work-hardened phase of silicon, where the stress-strain curve of the material changes somewhat from unworked crystalline silicon, or Si-I (pronounced "silicon-one"). So based on the morphology, a ductile grinding mechanism is dominant in poligrinding. It is preferred as well for rough grinding, it is a mixed mechanism of ductile and brittle grinding. This generates amorphous silicon, or a-Si upon interaction.

These two images show the results of brittle grinding and ductile grinding. Notice the chunks of material that have been ripped out due to brittle grinding. Ductile grinding tends to leave gouges in the material with extruded material immediately adjacent to the trench.

Poligrinding and rough grinding show multi-layer damage structures, which is the result of ductile grinding. The images on the right show the damage that occurs with both techniques. Notice the amorphous silicon layer in gold, the plastically deformed layer in cyan, the elastically deformed layer in magenta, and the undisturbed crystalline silicon in gray. Due to difference in load pressures, each layer in rough grinding samples is thicker than its counterpart in poligrinding samples. In rough grinding samples, dimples and sub- surface cracks caused by brittle grinding are irregularly distributed.

To summarize the grinding process for wafer thinning, there are two identifiable mechanisms: ductile and brittle grinding. In poligrinding, the ductile mechanism is dominant and in rough grinding, both ductile and brittle grinding occur. Both grinding processes create damage that extends for some distance into the silicon. The rough grinding process produces a damage layer of amorphous silicon that is about 70 nanometers thick, a plastically deformed layer of about 3.5 microns, and a stressed region of about 20 microns. Poligrinding generates much less stress. The amorphous silicon layer is only a few nanometers thick, and the plastically deformed and stressed layers are each approximately 2 microns thick.

Ask the Experts

October 18, 2015

Q: What are Base and Metal Layers?

A: Base layers are the layers which are implemented in the silicon substrate (like source/drain implants, VT implants, NWELL layer, etc.). Metal layers obviously refer to the mask layers associated with the back end of the process (like M1, M2, M1-M2 via, etc). In the EDA process process flow base layers are taped out first and then metal layers.

September 20, 2015

Q: Why do we use different materials in Solid Immersion Lenses (SILs)?

A: It has to do with the wavelengths we want to pass through the SIL. For example, a Si SIL works well for longer wavelengths like 1300nm (used for techniques like TIVA/OBIRCH), a GaAs SIL works well for mid-wavelengths like 1064nm (used for techniques like LADA), and a GaP SIL works well for shorter wavelengths (like those down in the visible range).

August 16, 2015

Q: I analyzed a customer return failure and the failure mechanism appears to be voiding due to intermetallic growth. What do you think happened to this part?

A: Based on the evidence, the part you're analyzing saw high temperatures for an extended period of time. We can't tell from the images when that might have happened though. It could have occurred during bonding (not likely, but possible), during some other portion of the assembly operation (also not likely, as you would have had many other failures), or during field use (more likely). You'll need to work with your customer to track down the root cause. Are other bond pads on this chip showing the same voiding?

July 19, 2015

Q: How does current-carrying-capability between Gold and Copper wire compare?

A: Both resistivity and melting temperature play a role in current-carrying-capability. Gold and Copper have somewhat different resistivities. Gold is 2.44e-6 ohm-cm, while Copper is 1.68e-6 ohm-cm. This means that Copper has about 1.4 times the current-carrying-capability of Gold. Gold and Copper have fairly similar melting temperatures, so melting temperature is not an important difference between the two metals.

June 21, 2015

Q: How fast does an underfill flow around the bumps or pillars on a device?

A: There are a number of variables involved in determining that number. They include: the viscosity of the underfill (which is dependent on the epoxy properties and the amount of filler particles), the size of the package, the number of bumps, the density of bumps (which is a function of their pitch), the height of the bumps, the temperature, other chemicals present (like adhesion promoters and flux), and so on. As a rough number though, a combination of substrate temperature, material, equipment and dispense process can show complete flow out under a 25mm square die with 60um gap in about 35 seconds.

May 17, 2015

Q: Are there chromium-free chemical etch recipes for decorating silicon?

A: Decorating silicon used to be a straightforward process using the Secco etch, Sirtl etch, or Wright-Jenkins etch. However, in recent years, a number of governments and municipalities have banned chromium due to its toxicity. A few etches like the Dash etch, FS Chromium-free etch and the Jeita/MEMC etch are chromium-free and will etch silicon, but their etch rates are too high to reveal defects in small areas and in SOI materials. Copper decoration in combination with preferential etching is a procedure that can used for the delineation of small crystal defects in bulk silicon and SOI. The crystal defects can be decorated using either Cu(NO3)2 - or LiNO3 solutions of varying metal concentrations. Experimental parameters such as concentration and volume of the solution used and annealing temperature for the decoration procedure would need to be developed and optimized for each fabrication process.

April 12, 2015

Q: I heard the term flying probe tester recently. What does that mean exactly?

A: Flying probe testers is a term used to contrast against bed-of-nails testers. In a flying probe test system, an on-board computer places the needles or probes over the appropriate locations on a Printed Circuit Board to make electrical contact. This allows better utilization of the tester resources, since one only sets down on pads of interest. It also removes the need for fixturing. In a bed-of-nails tester, the probe points are fixed, so one would need a fixture to probe on a particular package type as an example.

March 15, 2015

Q: I have a HAST Failure in a package with copper bond wires and a silver plated lead frame. Is there any way I can eliminate this type of failure?

A: This is a difficult situation, because you are working with two metals that exhibit galvanic corrosion characteristics. The best solution is to change out one or both of the metal surfaces with something that is less susceptible to corrosion. For copper wires, one could switch to Palladium-Coated Copper (PCC) wire, and for the silver-plated leadframe, one could switch to a material like Nickel-Palladium-Gold (NiPdAu) as a coating on the leadframe.

February 16, 2015

Q: I have heard the term NSOL and NSOP. What do they mean?

A: NSOL and NSOP mean Non Stick On Lead and Non Stick On Pad respectively. Lead refers to the exposed leadframe, and Pad refers to the bond pads on the integrated circuit. This can happen for several reasons, but typically occurs when the die attach bake process releases volatile compounds, which coat the leadframe and bond pads. This can interfere with the bonding process, leading to a wire bond that doesn't bond correctly to the bond pad or lead frame.

January 18, 2015

Q: Where do we use melamine in the IC packaging process?

A: Melamine is a material used for the cleaning of mold stain deposited during the molding of epoxy molding compound for encapsulation of leadframe products like capacitors, resistors or semiconductor IC chips. This allows thermosets and thermoplastics to easily come out of the mold after molding.

December 21, 2014

Q: Why do engineers use more than one algorithm to identify outliers?

A: The reason stems mainly from the type of distribution related to the parameter used for outlier identification. For example, if we use diode breakdown voltage as an identification parameter, the distribution of breakdown voltages is typically a normal distribution. That means that algorithms like the 3-Sigma algorithm will work well. On the other hand, if we use a parameter like IDDQ, the distribution for IDDQ is typically right-skewed (a tail of data that extends to higher currents moreso than to lower currents). In this case, an algorithm like Tukey or CPKn will tend to do a better job. Many engineers actually prefer the CPKn algorithm when the tails are significant.

November 16, 2014

Q: I think IDDQ would be a useful test for us to be able to localize defects, but the IDDQ defect distribution lies within the main population and is difficult to separate out. Do you have any ideas?

A: You might try using other parameters like temperature and voltage to try and separate the defects out of the population. For instance, you can plot the distribution of IDDQ at 25C against the distribution at 85C, or plot the distribution of IDDQ at 1.5V against the distribution at 2.0V and look for outliers that way.

October 19, 2014

Q: How do you adequately protect high speed signal interfaces like LVDS interfaces from ESD and EOS?

A: This is a difficult task. The problem is that high speed signal interfaces require high performance transistors, which are small and sensitive to overstress. This means that to protect them from overstress events, particularly overstress events like charged device model ESD pulses, one must place resistors on the gates of the input transistors, or in series with the output. Unfortunately, this will slow down the operation of the circuits. This places the designer between a rock and a hard place. If one really needs a combination of high speed with additional protection, then one may need to consider other interface schemes that are not direct electrical connections, like optical connections or RF energy connections.

September 21, 2014

Q: What is the near-threshold voltage computing?

A: Near-threshold voltage computing is a technique for operating transistors at lower voltages to try and minimize the power-switching product. As one operates at lower voltages, the switching speed goes down, but the power goes down even more so. This effect ends as the power supply approaches the sum of the n-channel and p-channel threshold voltages of the transistors though. Researchers are looking into applications for this technique as it may facilitate low levels of processing while saving power. Rob Aitken of ARM discusses this technique in more detail in this presentation. http://semiengineering.com/tech-talk-near-threshold-computing-2/

August 24, 2014

Q: What is the p-value term in an ANOVA (Analysis of Variance) calculation?

A: The P value tests the null hypothesis that data from all groups are drawn from populations with identical means. Therefore, the P value answers this question: If all the populations really have the same mean, what is the chance that random sampling would result in means as far apart as observed in this experiment? If the overall P value is large, the data do not give you any reason to conclude that the means differ. Even if the population means were equal, you would not be surprised to find sample means this far apart just by chance. This is not the same as saying that the true means are the same. You just don't have compelling evidence that they differ.
If the overall P value is small, then it is unlikely that the differences you observed are due to random sampling. You can reject the idea that all the populations have identical means. This doesn't mean that every mean differs from every other mean, only that at least one differs from the rest.

July 27, 2014

Q: I am trying to determine the percentage of chromium in a SiCr fusible link resistor using Energy Dispersive X-Ray Spectroscopy, but I am seeing a very low percentage (1-2%). How much chromium should be in the SiCr resistor?

A: The typical number is between 15 and 35%. The reason you are seeing such a low percentage is probably due to the fact that the SiCr resistor is very thin, and the interaction volume of the SEM is penetrating well beyond the material, causing you to see more of the silicon in the SiO2 and substrate. The resistor film is usually around 10nm thick, which means the vast major of the beam penetrates beyond the resistor.

June 29, 2014

No Ask the Experts section this month.

May 30, 2014

Q: I seem to recall that the makers of PIND equipment had a tape for gathering loose material when using the PIND system with the top perforated, or with the top open as a cleaning step. Who supplies that tape?

A: There really isn't a "special" brand of tape for this work. Most analysts will simply use a heavy duty double-backed adhesive tape from a manufacturer like 3M. The main issue is examination of the particles. Double-backed tape will outgas when placed in the SEM, so pump down, especially in a Field Emission SEM, where one requires lower vacuum levels. For specific recommendations though, one might contact Spectral Dynamics (www.spectraldynamics.com). They sell acoustical tape circles that might work well for this applications.

April 27, 2014

No Ask the Experts section this month.

March 23, 2014

Q: What is the Kooi effect?

A: The Kooi effect is also known as the white ribbons effect. It was first documented in the mid-1970s by Else Kooi, who worked at Philips Research in the Netherlands. It is the formation of a nitrogen-rich layer near the gate interface. Water oxidizes the silicon nitride mask layer, creating ammonia (NH3). The ammonia can then diffuse to the silicon interface where it forms a silicon nitride or nitrogen-rich oxide layer. This can interfere with gate oxide growth, making the gate oxide too thin in regions where the nitrogen-rich layer exists.

February 23, 2014

Q: We are looking to develop the EBIC technique on our FA lab (we have a Kleindiek system) mainly on Silicon power device; any help or comments on our activities would be greatly appreciated (defect detected, technical details, limits, advantages over other methods...)

A: This is an overlooked technique that is great for isolating failures. It can be especially useful in conjunction with a nanoprobing solution in the SEM, like you mention. Another approach is to use an AFM Probing System (Multiprobe is a manufacturer of this type of system). If you do a lot of fault localization, then this can be a great way to isolate things further. We discuss this technique in our Online Training System, and can do a 1-day course on this topic as well.

January 26, 2014

Q: Will SOI be the path forward for continued CMOS scaling?

A: This is a highly complex question and the source of a lot of debate within the industry. Currently, the thinking is that FinFET technology provides a better path forward because the fin structure permits better channel electrostatic control. However, Fully Depleted SOI (FDSOI) is a less complex process, and would provide a platform for other advances, like Monolithic 3D integration and Silicon Photonics. SOI uses a more expensive substrate, so cost-sensitive applications may not be able to go this route. Stay tuned over the next several years to see how this will play out.

December 22, 2013

Q: How accurate is an IDDQ vs. VDD curve trace in determining the actual defect on an IC?

A: We actually discuss this test and defects in this month's Technical Tidbit. IDDQ vs. VDD can help the analyst separate opens from shorts, and identify various types of shorts, but the accuracy level is only around 85% or so. Although IDDQ is a great test for establishing the direction of an analysis, it is even less accurate by itself in determining what the actual defect will be. One will need further analysis to identify the actual defect.

November 24, 2013

Q: Why do some suppliers sell Copper Alloy lead frames rather than just pure copper lead frames?

A: A copper alloy lead frame (like Cu-Fe, Cu-Cr, Cu-Ni-Si, or Cu-Sn) can have better hardness properties which reduce bending and deformation during the assembly process and in more aggressive thermal cycling situations. The challenge is to increase hardness without increasing the resistance too much, since an element alloyed with copper will increase the resistance.

October 20, 2013

Q: Why are IC test floors so loud?

A: The air conditioning and tester fans create the noise. Automatic Test Equipment to test high performance ICs use a lot of power. These systems need to be able to produce and capture accurate waveforms at high frequencies. This requires specialized circuits that dissipate a lot of power. When you couple this with the fact that a test system might require several hundred of these circuits, and the fact that there might be dozens of testers on a test floor, a lot of heat must be dissipated. A round number for a tester might be 10 watts per channel times 400 channels. Therefore, 20 testers would dissipate 80,000 watts. If the A/C were interrupted on one of these test floors, the temperature would climb 40 °F (22 °C) in a matter of 15 minutes.

September 22, 2013

Q: I hear a lot of discussion about NBTI (Negative Bias Temperature Instability). Is PBTI (Positive Bias Temperature Instability) a problem as well?

A: It can be in High-K Metal Gate technologies, but it is not a big issue in circuits with oxide or oxynitride-based gate dielectrics. Mikael Denais and a team from ST Microelectronics did a nice study on this issue back in 2004, and determined that while PMOS NBTI can lead to changes in threshold voltages of as much as 8%, NMOS PBTI, NMOS NBTI, and PMOS PBTI normally exhibit changes of less than 1%. Researchers do see bigger shifts in PBTI with High-K Metal Gate transistors, and they are actively studying this phenomenon.

August 25, 2013

Q: What are some factors that affect the activation energy of TDDB?

A: The answer to this question has much to do with the processing conditions for the gate dielectric. For example, activation energy plays a bigger role when the dielectric layer is thicker. When the layer is thicker, the thermal energy imparted to the bonds in the dielectric are more significant. This is reflected in models like the Thermochemical E model. When the gate dielectric is ultrathin, the bonds in the dielectric are fairly few in number, so other factors play a bigger role, like the ionization and movement of atoms in the electric field. Temperature can still play a role, but it is a more minor role. TDDB for BEOL dielectrics is somewhat different. Here, the movement is more related to the drift of copper atoms along interfaces in the dielectric. This behavior is temperature-dependent, so there is an activation energy for this process.

July 21, 2013

Q: Our application has to withstand the following conditions during its lifetime for 15 years:

100,000h @ 20°C
5,000h @ 60°C
100h @ 100°C

We performed a storage test with this application, running for 500 hours @ 150°C. How many years (real life) we have simulated with this storage test refer to our real life conditions? (Ea=0.6eV; Tuse=20°C, 60°C and 100°C; Tstress=150°C)

A: This simple spreadsheet shows how one might figure this out. We need to determine the acceleration of your application under the 3 different temperature regimes, compared to your stress test. These numbers appear in the column second-to-the-right. They are calculated using the Arrhenius acceleration factor formula. One can then multiply the acceleration factor by the number of hours to get the effective acceleration hours. In this instance, the total use condition environment is equivalent to 137 hours at 150°C using your activation energy of 0.6eV.

Hours Temp (C) Temp (K) Acceleration Compared to 150°C Effective Acceleration Hours
Use Condition 1 100,000 20 293 AF 0.000674897602668 67.49
Use Condition 2 5,000 60 333 0.011709486190678 58.55
Use Condition 3 100 100 373 0.110163111408894 11.02
Total Use Conditions 137.05
Stress Test 500 150 423
Activation Energy 0.6
k 8.62E-05

June 23, 2013

Q: How do I etch down to the polysilicide layer without damaging it?

A: For failure analysis purposes a recipe like this would work decently. It's based off of one of the main patents for opening contact windows over titanium silicide.

Power: 200W
Pressure: 100 mTorr
Gas 1 CHF3: 50 sccm
Gas 2 CF4: 10 sccm
Gas 3 Ar: 100 sccm

TEOS Etch Rate: 494 Å/min
Annealed TEOS: 450 Å/min
Photoresist Etch Rate: 117 Å/min
Thermal Oxide Etch Rate: 441 Å/min
Silicon Etch Rate: 82 Å/min
TiSi2 Etch Rate: 1 Å/min

The etch rate for CoSi or NiSi might be somewhat different, but I think this would give sufficient selectivity to expose the polysilicide layer cleanly without damaging the layer. Where problems might occur is if there are silicon-rich regions in the polysilicide, they can be leached out by the RIE process.

May 12, 2013

Q: Why is there the option to perform Latchup Testing at both room and hot temperatures? When should I test for latchup at hot temperatures?

A: JESD78 defines two classes of Latchup testing: Class I and Class II. Class I testing is at 25°C, whereas Class II testing is at the maximum operating temperature of the component. For most components, latchup susceptibility increases with temperature, so it makes sense to test at high temperatures, especially if the end application includes scenarios where one might operate at high temperatures, like in an automobile for example. Many companies will perform latchup testing at both 25°C and maximum operating temperatures just to be on the safe side.

April 14, 2013

No Ask the Experts section this month.

March 17, 2013

No Ask the Experts section this month.

February 17, 2013

Q: Today, you see a lot more equipment using Dry Pumps. Why is this?

A: This is primarily due to the fact that oil-based pumps suffer from a phenomenon known as backstreaming. Oil vapor can be sucked back into the system chamber. In a wafer fabrication tool, this can lead to contamination on the wafer surface, which can interfere with processing and limit the yield. In an analytical tool like a scanning electron microscope, the oil vapor on the surface can be carbonized or polymerized by the electron beam, creating a thin layer that interferes with imaging. Furthermore, this material is difficult to completely remove. The best way to avoid these problems is to use a dry pump instead.

January 20, 2013

This time, I thought we might answer a question posted to the Failure Analysis Group on LinkedIn:

Q: Recently we received a PCBA (printed circuit board assembly) with a detached BGA (ball grid array). The pads look black in an optical microscope, so we refer to this as the "Black Pad" issue. The analysis results revealed mud crack symptoms and severe corrosion activities on the Nickel layer of the PCB pads. What might be causing this?

A: You might want to see if you can determine the phosphorus content present on the surface of the pads. The black discoloration definitely sounds like corrosion, but it would be good to know what the other element in the corrosion product is. Excess phosphorus on the pads can cause this type of problem.

December 23, 2012

Q: MM and HBM are common requirements for our products (power amplifiers/low noise amplifiers), but is CDM also a must during qualification?

A: CDM is an important test method when the products you produce will go through a lot of automated assembly and testing. I am not sure if that is the case for your products. You may have to check with your product engineers to determine which markets your parts go into. In general, power amplifiers would not be as sensitive to CDM damage as low noise amplifiers, but most amplifiers have ESD-sensitive inputs.

November 25, 2012

Q: Machine Model (MM) and Human Body Model (HBM) are common ESD testing requirements for power amplifiers/low noise amplifier, but is Charge Device Model (CDM) also necessary during qualification?

A: CDM is an important test method when the products you produce will go through a lot of automated assembly and testing. I am not sure if that is the case for your products. You may have to check with your product engineers to determine which markets your parts go into. In general, power amplifiers would not be as sensitive to CDM damage as low noise amplifiers, but most amplifiers have ESD-sensitive inputs.

October 28, 2012

Q: I am considering signing up for your Online Training System, but have a question. If I have a question about the materials, is there a way to contact anyone?

A: Yes there is. The author of the presentation can be directly contacted through the email link that is embedded in the presentation. In the upper left under the picture of the author, simply click on "email" and the interface will present a link allowing you to email the author.

September 16, 2012

Q: Are muons a threat to computing systems? Should I be concerned about them when I formulate reliability plans for our components?

A: The short answer is "Yes", but the answer is somewhat more nuanced. Yes, muons can be a problem. Muons are charged subatomic particles with a mass of approximately 200 electrons. Although their cross-section is not very large and they're not as common as alpha particles, their ability to deposit charge and disrupt electrical operation is substantial, much more so than alpha particles. However, as devices scale down, this problem appears to be lessening somewhat. A good place to learn more about their effects on circuitry is through recent papers at IRPS and NSREC. I would encourage the reader to start with the Vanderbilt paper presented in 2011 at IRPS.

August 19, 2012

Q: My sample appears to have a burned-in rectangle after I image it for a period in the SEM. What is happening?

A: Several things come to mind. I would examine the problems in this order. One, your sample might simply be charging. This can happen if you image a dielectric layer with a higher accelerating voltage for some time. If you remove the sample from the chamber, put it back in, and the rectangle is gone, this is likely what's happening. Two, the problem could be due to sample preparation. If you don't get the surface completely clean, it is possible for the electron beam to charge a residue layer, or polymerize a residue layer, creating this burn-in effect. To correct this problem, try performing ion beam milling. The oxygen or argon bombardment will remove the residue layer, eliminating this problem. Gatan and other manufacturers sell equipment that can do this. And three, the problem could be due to roughing pump failure. As a roughing pump fails, oil can potentially backstream into the chamber and on to the sample surface. This can be corrected by rebuilding or replacing the roughing pump.

July 22, 2012

Q: What is the coefficient of thermal expension for BT (Bismalemide Triazine)?

A: It is approximately 15 ppm/C in the X and Y directions, and approximately 52 ppm/C in the Z direction. This means that it matches the coefficient of thermal expansion of copper relatively well in the X and Y directions, but not in the Z direction. Plated through holes comprised of copper may be less reliable on a BT substrate. Manufacturers and designers primarily like BT because it can be manufactured with a high glass transition temperature, and it exhibits a low dielectric constant.

June 10, 2012

Q: Can etching of the polyimide layer to form windows for the bond pads on a circuit subsequently create poor contact for bond wires?

A: Yes, this has been observed in the past. The etch residues and hydrolysis products affect the surface of the bond pad, degrading its adhesive properties. An early paper that discussed this problem is C.G. Shirley and M.S. DeGuzman, "Moisture-Induced Gold Ball Bond Degradation of Polyimide-Passivated Devices in Plastic Packages", Proc. IRPS, pp. 217 - 226, 1993.

May 13, 2012

Q: Is there a way to do a selective wet etch so that only a portion of the chip is etched?

A: Yes there is. You can deposit photoresist, selectively expose it, develop it, and then etch in the area or outside of the area, depending on the type of photoresist used. The paper that discusses this technique is called "Micro-Control of Photoresist Deposition for Failure Analysis of Microelectronic Circuits", presented by K. Hussey, N. Dickson and J. Reyes at ISTFA in 1992.

April 15, 2012

Q: I have seen graphs (like I show to the right) where engineers have plotted median lifetime hours (log scale) as a function of temperature (linear scale), drawn a straight line through it, and then used the slope to determine the activation energy. Is this a correct way to calculate activation energy?

A: Normally, one would plot the temperature axis as one over T on a linear axis. By plotting T on a linear axis, you not properly calculating the activation energy when drawing a straight line through the data.

March 18, 2012

Q: I need to distinguish unambiguously between LOCOS and STI, particularly in the case when you can not compare between them, but need to know which type. The "birds beak" effect is not very clear in most cases. Please, advise what other ways to certainly identify each of the types. I will appreciate your thoughts.

A: A couple of thoughts come to mind. Usually the trench for STI will be etched deeper into the silicon. Remember that LOCOS consumes silicon, so about 45% of the oxide grows down into the silicon while the upper 55% will be above the original surface. The trench sidewalls will be steeper than the LOCOS sidewalls. Of course, you'll need to cross-section the device to see these items. For a top-down assessment you might be able to determine this optically, but it will be difficult on a modern technology. Because the oxide extends above the surface, features on the oxide may not be in focus at the same time as features directly on the silicon. You could possibly see this effect on the polysilicon while viewing at high magnification.

A reader wrote in concerning last month's "Ask the Experts" column and brought up a good point regarding interpretation of the I-V curve. Here is his response:

I think you missed the obvious on your answer in the "Ask the Experts" question. It could be a lot of things, but if it was a CMOS device, then one thing that should be noted is that a CMOS inverter always shows this effect. The NMOS and PMOS transistors have their gates tied together in the CMOS inverter. If the common gate starts at zero and is ramped up, initially, the PMOS transistor is on but the NMOS is off showing little current through the two transistors in the inverter. As the gate voltage increases, the NMOS transistor turns on and current is then pulled between VCC and GND. Eventually, the PMOS transistor will turn off reducing the power supply current again. Thus, it is a common occurrence to see this "middle" area with higher current. The actual circuit analysis will be much more involved, so the full answer can not be given without knowledge of the circuit, but high current with the voltage between the NMOS Vt and the PMOS Vt is not unusual.

February 19, 2012

Q: I am seeing an I-V curve for an IC between VDD and GND that looks like this (see figure to the right). What creates the momentary drop in the upper right?

A: Several things might cause this behavior. One item you might want to check is to see if you have good continuity. Intermittent continuity could create this type of curve. A second possibility (more likely) is that you are attempting to power up a device without properly tying the input pins to either ground or VDD. You should tie all floating inputs to either ground or VDD to prevent unstable leakage during power-up. A third possibility is that the IC is experiencing some type of internal bus contention at lower voltages. One side of a bus may power up into a state opposite the other side of the bus, causing increased current. This can then resolve itself as the voltage increases on the internal components.

January 22, 2012

Q: Currently, I have an issue with a BJT IC that failed after reliability. The failures recovered after we subjected them to baking. We did put these devices back into the chamber in the hope of simulating the failure again. But no failures were detected. You can say that baking has irreversible effect on these devices.
Do you think this is a case of surface charge? How can I confirm further if surface charge is the cause here?
Hope you can spare some time to help me with this issue.
Thanks a lot for your help.

A: It could still be a charge-related problem, but the charge may not have occurred in a way that a burn-in could activate. For example, an overstress event that avalanches the collector-base or emitter-base junction can sometimes place charge on a junction. If the bias is correct during the test, or if the overstress event occurred at the end of the reliability test during the electrical testing, then the charge might be present during the test. If you then did a bake, you would re-distribute the charge and make the leakage go away. If you put the devices back in the chamber, but there was no overstress event, there would not be any failures.
Examining the I-V curves and a schematic of the bias in the reliability test would also be a useful thing to do. It might give you some insight into where the overstress might have originated and how it might have been detected at electrical test.

December 18, 2011

Q: How do I keep from losing a very small die when I decapsulate it with sulfuric acid?

A: Probably the best way to keep from losing a very small die is to put the package in a fine wire mesh bag and dip the bag in the sulfuric acid. That way, the die and lead frame stay contained. You can then dip the bag in isopropyl alcohol to stop the etch, rinse the bag in deionized water, and retrieve the die and lead frame under a low power microscope.

November 21, 2011

Q: How can I limit the breakdown damage when an oxide is stressed in a power MOSFET device?

A: Use a current limiting resistor or set a lower compliance limit on the SMU. A more active monitoring circuit may be needed if the FN tunneling current is already significant.

October 23, 2011

Q: Is oxidation-enhanced diffusion prominent or negligible?

A: The answer depends on the dopant elements involved. Oxidation generates excess silicon self-interstitials, which enhance the diffusivities of atoms that diffuse with a significant interstitialcy component. This includes Boron, Phosphorus, and Arsenic. It retards Antimony, which diffuses primarily by the vacancy mechanism.

September 25, 2011

Q: What types of techniques can be used to highlight bond pad cratering?

A: One technique that can highlight bond pads for cratering using an optical microscope is nickel decoration. The aluminum bondpad is etched away, and the chip is placed in a nickel plating solution for several minutes. The nickel will first adhere to the cracks, providing contrast in the optical microscope.

August 24, 2011

Q: I need the actual info on: MSL 2 sample (Rel stress soaking: 85°C/60%RH, 168hrs). Floor life is 1 year under 30°C/60%RH storage. What is the floor life if storage under 30°C/70%RH?

A: The best way to make this calculation is to use Peck's Formula to calculate an acceleration factor.

The AF (ratio of TF values, 70%RH/60%RH) = (RH70%/RH60%)-a * exp([Ea /k](1/ T70% -1/ T60%])

The temperatures are the same between the two, so only the humidity is a factor. We'll use 2.7 for a (the humidity exponent) – a typical value for this calculation.

AF (70%/60%) = (70/60) 2.7
AF (70%/60%) = 1.516

So the floor life storage would be 1 year / 1.516 or 0.6595 years (7.914 months) at 70%RH.

July 19, 2011

Q: We are using the growth equation (see Excel GROWTH function for details) to model degradation in InGaN laser diodes. Is this approach acceptable for prediction purposes?

A: Using the GROWTH function in Excel presumes that the degradation process will be slow and non- catastrophic. While this approach might be acceptable on a mature process line where no catastrophic degradation occurs, it is quite dangerous to make this assumption across all device types or technologies. Some devices can degrade gradually for a period of time and then exhibit a dramatic, or catastrophic decrease in output.

June 22, 2011

Q: How can I limit the breakdown damage when an oxide is stressed in a Power MOSFET device?

A: Use a current limiting resistor or set a lower compliance limit on the SMU. A more active monitoring circuit may be needed if the FN tunneling current is already significant.

May 27, 2011

Q: Is there a standard for SEU testing?

A: Yes there is. JEDEC issued JESD-89 in 2007 to cover SEU testing. There are several parts to the document; be sure to read each one so you know how to apply the testing to your situation.

April 29, 2011

Q: What is the difference between MTBF (Mean Time Between Failures) and MTTF (Mean Time To Failure)?

A: At first glance, the two terms seem to be the same, but there is a fundamental difference in how they are applied. MTTF assumes that the system is not repaired, so MTTF is basically the integral from 0 to infinity of the fraction of all failures for a given time with respect to time (add the equation). MTBF assumes the system can be repaired, and is repaired instantaneously. The equation for MTBF adds the time variable explicitly into the integral. Therefore, MTTF is a more appropriate variable for a system or component that cannot be repaired, like an IC, whereas MTBF is more appropriate or systems that can be repaired, like an automobile, or PCB.

March 25, 2011

Q: What types of techniques can be used to highlight bond pad cratering?

A: One technique that can highlight bond pads for cratering using an optical microscope is nickel decoration. The aluminum bondpad is etched away, and the chip is placed in a nickel plating solution for several minutes. The nickel will first adhere to the cracks, providing contrast in the optical microscope.

February 17, 2011

Q: I am detecting sulfur on the top of packaged devices as well as on the bond pads of printed circuit boards in our manufacturing process. What might be causing this contamination?

A: There are several common sources of sulfur in PCB manufacturing and assembly. They include: outgassing of elastomers vulcanized with sulfur, contamination in the PCB board itself, sulfur in the solder resist material, stop-off lacquer, contamination from paper or paperboard (cardboard) materials, and industrial environments or city environments with high sulfur or sulfide concentrations.

January 20, 2011

Q: What is the difference between troubleshooting and failure analysis?

A: Troubleshooting and failure analysis have quite a bit of overlap in the semiconductor industry. Troubleshooting usually refers to the process of localizing the problem, whether that be on a chip, inside an electronic component, or within a system. Troubleshooting normally implies finding the problem, and potentially fixing or replacing the component with the problem. As such, we normally think of troubleshooting without regards to fixing the underlying cause. Failure analysis is usually a defined (quite often required) activity that involves not only troubleshooting, but investigation into the root cause of a problem as well as development of a corrective action. Therefore, in failure analysis, we work to fix the underlying cause.

December 16, 2010

Q: I was at IEDM last week and heard people talking about the problems with DIBL and how it affects the scaling of transistor. Can you explain what DIBL is and how it is a problem?

A: Drain Induced Barrier Lowering or DIBL is an effect in MOSFETs where the threshold voltage decreases at higher drain voltages. In traditional technologies where the channel length is longer than 50nm, this typically results in an increase in drain current at a given voltage. This graph shows an example of this effect. While this effect may seem to be an advantage at longer channel lengths, since the given current at a particular drain-source voltage (VDS) is larger, it actually becomes a detriment in very advanced technologies.

As engineers continue to scale transistors, they have moved toward a different definition of current in order to estimate performance. Because the transistors in a CMOS gate never reach their peak current (given by ION), engineers instead use an IEFF value which corresponds to 50% of VDD. For a given IOFF and ION level, the transistor with the higher DIBL effect actually exhibits a lower IEFF value. The lower drain current occurs because the DIBL effect is more pronounced at higher drain voltages. Therefore, when one normalizes the ION values with and without DIBL, the net effect is a lower IEFF at 50% of VDD like we show in this graph. This is a fairly new revelation to device engineers, and requires some thinking as to how to address it at the 22nm nodes and smaller.

November 15, 2010

Q: Sometimes I see i/(n+0.5) used for median ranks, and other times I see (i-0.3)/(n+0.4) used for cumulative probability in probability plots. Is one better than the other?

A: The second formula (i-0.3)/(n+0.4) is the more accurate approach. If you scale down to a sample size of 1, it correctly resolves to 0.5 for a cumulative probability. i/(n+0.5) resolves to 0.66, which is not as accurate. If you are doing calculations by hand, then i/(n+0.5) is quicker, but since most people will use a program like Excel or Relex to do these calculations, it is better to use (i-0.3)/(n+0.4).

October 27, 2010

Q: I have a question regarding package decap and copper wires. I am experiencing problems keeping the copper wires from being attacked while etching open the packages.

A: Packages with copper wires can be quite difficult. The success of opening a package with copper wires is directly related to the type of encapsulant used and the gauge and density of copper wires used in the package itself. The more dense the wires, the more difficult the application. For example, LSI Logic created a package that had 3 rows of bonds in a BGA. It is almost impossible to clear all of the encapsulant material from between the copper wires and expose the bonds without some damage to the wires. The best way to approach packages with either unpassivated copper on the surface of the die or copper wires is to start with a 3:1 mix of 90% fuming nitric acid and 20% fuming sulfuric acid at 37-40 degrees Celsius. The etch will be longer, but the chance of copper preservation is far better.

September 23, 2010

Q: We would like to purchase Liquid Crystal and the FMI compound, but we don't know where we can buy it from. I would appreciate if someone can give me the name of a company that sells LC and FMI.

A: You can purchase both materials from Accelerated Analysis. http://www.acceleratedanalysis.com/.

Q: I am having difficulty etching plastic packages. I have a package that does not etch open using either nitric or sulfuric acid. Are there other acids/chemicals that can be used on such packages?

A: Usually, problems experienced with decapsulation of plastic packages can be linked to one of two things: 1. Poor fixturing and/or 2. Wrong recipes.

To eliminate the former, replace any gaskets that are worn, etched, or misshapen. You can also use, rather than a stack of gaskets, a single monolithic or pocket gasket that encompasses both the location of the part and an opening that defines the area of etch. Pocket or monolithic gaskets are the best way to define the area of etch and to hold the part. Pocket gaskets are critical with small packages.

We have never run into a plastic package we couldn’t open using the proper recipe. Normally one would use a 20% fuming sulfuric acid to open a thermal plastic such as those used with T0-220 packages or some BGAs that give off lots of heat when in use. Some of old encapsulants, like those from Conexant were like cement and took long times to open but would yield to 20% fH2SO4 in time and at 230-250 degrees Celsius. Remember, good decapsulation is like good cooking – you need the proper recipe and the proper utensils.

August 24, 2010

Q: What is the best way to non-destructively check for and isolate bond wire to scribeline shorts?

A: A pin-to-pin electrical continuity test in conjunction with the magnetic current microscope, or SQUID microscope, is the best approach for detecting and localizing shorts in a package. While this is an expensive technique (the Neocera Magma SQUID tool runs more than USD 500k), it is probably the best approach, since other techniques like x-ray radiography do not definitively show short locations.

July 15, 2010

Q: You mentioned a couple of techniques, namely shroo and shrunk clock, that people here are not real familiar with. Can you explain these techniques in a little depth, or, even better, show real-world application of them?

A: Shrunk clock is a term occasionally used to refer to the shortening of a clock cycle while performing a speed path test. For example, let's assume an IC is operating at 50MHz. The clock cycle would be 20 nsec. If we increase the frequency to 66MHz, we have in essence "shrunk" the clock cycle to 15 nsec. So, a shrunk clock is another way of stating that we sped up an IC or a path within an IC.

Shroo is a contraction of shmoo and shrunk. Normally, a shmoo plot involves the entire IC. The term shroo refers to a shmoo plot on just a portion of the IC. For example, one can generate a shmoo plot for a particular speed path by changing the speed of the IC on one axis in the shmoo plot and the voltage (or possibly temperature) on another axis.

June 15, 2010

Q: What are the standard practices for implementing 2nd level qual?

A: Qualification requirements vary considerably by package, application conditions, and lifetime requirements. There is a balance between a standard set of requirements and those targeted at a specific customer’s need. The trends have been re-use of existing data based on structural similarity and failure mechanism-based testing, so we do the tests that are most likely to catch the failure mechanisms we expect based on FMEA analysis. As a result, we need to become experts in failure mechanisms.

Second level tests relate to attachment, and are defined by JEDEC specs JESD122 –B105 (Fatigue) B104 (Shock) B103 (Vibration) etc., and may include bending, twisting, etc. Your customer may have some specific application-related issues. The application board construction, layout, materials, and processing are critical elements. However, on the IC supplier side, standard boards must be used, typically with a board layout designed to be testable (Daisy Chain), diagnosable, and sometimes capable of using Event Detection (continuous monitoring hardware).

Structural similarity is used to determine how much existing data can be used to qualify a new product/package, process, or part in a new application. Qualifying a device requires knowing what factors are important. Historically, this was formalized in CPCN (Critical Process Change Notifications) and usually required custom qualification. By applying structural similarity rules, the same reliability assurances can be achieved faster and cheaper. The process should be defined in a company’s qualification standards and qualification reports based on structural similarity should state the justification why that data is applicable. Knowledge is required both to make the right decisions and to document that decision to the (potential) customer.

So how do you determine the rules for structural similarity in order to decide when qualification data from one product can be re-used to qualify a different product? First, you must know the important failure mechanisms and what factors make them worse or better, preferably using some model. Obtaining this data requires reliability stressing to failure and failure analysis to determine root cause and causative factors. Normally, the stressing uses test chips test boards, serial connected pins optimized for simple stressing and analysis. Results can be used to calibrate the reliability models, including finite element analysis. Internal data is preferred. Although published data can also be used, the details can be sketchy. Not all knowledge comes from these test vehicles.

Any failure in stress or field use can offer insight into the failure cause. Out of this knowledge, some general rules can be developed. For example, below are some general observations for cyclic fatigue testing that might guide structural similarity rules. With more specific data, the rules could be made more specific.

Gull-wing parts: not much concern about solder fatigue for normal commercial applications, nor for drop test. By design, these failures are not worst case. Something else will fail first.

Substrate package fatigue: larger packages are worse, smaller solder volume is worse, finer pitch is worse, partially populated ball location can be critically layout dependent. Less important are wires, die stack, chip coat.

Leadless: similar to substrate packages.

PackageLess (e.g. WLCSP): here foundry, process, technology node, UBM and materials are the main factors.

Board factors: can be even more critical – for example, clamping of boards at the edge is bad. Components near large features can be a problem; thicker substrates are usually better. These, however, are outside the control of the IC vendor.

May 28, 2010

Q: Is there difference in 2nd level qual between BGA and QFN?

A: Some of the same factors apply, but the packages are very different. Differences include lead free or not, solder process, standoff from board, dimensions, and pitch. QFN is much smaller, is made from different materials, and has a different construction, pitch, aspect ratio, etc. A lot of data is necessary to justify a relationship with much confidence. For more information, please see the following resources: Paper on the robustness process, ZVEI, Spreadsheet template to use in evaluating robustness factors.

April 29, 2010

Q: Why is Latchup testing sometimes performed at high temperatures?

A: Latchup depends on temperature, as shown by several studies of electrically induced latchup by Shoucair and Kolasinsky. The triggering current for electrically induced latchup decreases more than a factor of two as the temperature of latchup test structures is increased from 300 to 400 K. The main reason for this dependence is the increase in well resistance (it approximately doubles), with some additional contribution from the decreased forward voltage at high temperature.

March 29, 2010

Q: Would IDDQ help identify "weak" wire bonding? We have undetectable micro-cracks in our bonding that starts normally (e.g. part passes) but fails after temperature cycling. Do you have any ideas on how we might non-destructively & quickly test them to screen out the weak or "walking wounded" ones? I don't think TDR would be sensitive to this reliability problem (at least until the crack gets large).

A: It is possible that the Neocera Magma SQUID tool can detect weak wire bonds. The SQUID tool uses a sensitive high temperature superconductor detector to examine low level magnetic fields non-destructively. When the current necks down to a small region to get by a crack in a PCB, the current narrowing causes a dipole moment in the SQUID image which is visible. It's possible the same thing could happen with a bond wire. Good luck!

February 28, 2010

Q: I’ve heard that nitric and sulfuric acids behave differently with silicon/CMOS and GaAs technologies. Basically, one or the other acid destroys one (or the other) die. Do you know which acid is compatible with which die type?

A: Sulfuric acid tends to be more of a problem with GaAs. There is an etch system based on Sulfuric-Hydrogen Peroxide-Water for GaAs. If you can keep any oxidizing agent away (and nitric might act as one in this case if you mix the two) then you shouldn't be etching the GaAs substrate at an appreciable rate with sulfuric acid. In my experience, the bigger problem is etching the metals on the die. Both sulfuric and nitric in conjunction with water will etch aluminum.

January 14, 2010

Q: For conductive die epoxy, is it possible for the epoxy to become non-conductive? Is the epoxy conductive to X,Y, Z direction while grain size of silver is connected in specific direction? I believe the epoxy is a silver small grain size in liquid form. The liquid is non-conductive. Is this correct? If so, how does the epoxy become conductive?

A: Conductive epoxy adhesives usually set up their conductivity in a planar manner. Silver additive is normally in a flake format and forms a set of platelets that provide that planar structure. Cure shrinkage of the base epoxy resin compresses the silver particles to make mechanical contact with each other.

Losing conductivity could result from (1) thermomechanical delamination, (2) poor or no initial curing, or (3) separation of silver through either (a) initial resin bleed or (b) incomplete pre-mixing.

December 08, 2009

Q: How do you calculate the EM lifetime using the SWEAT test structures when the metal width is not uniform, alternating between narrow and wide segments? What is the normal EM failure location at SWEAT test structures?

A: The EM lifetime is normally calculated as a time to a percent increase in resistance in the structure (maybe 10%, or some other number). Given the temperature that you tested and the current density, you can then use Black's equation to project down to use conditions. The big problem with the SWEAT structure is that it does not replicate the metal layout on an IC, so most people use ASTM structures or other via-blocked structures that replicate the metal layout on a chip more effectively. The normal failure location will be at the beginning of a narrow segment based on the directions the electrons flow. Thus, if the electrons flow left to right in the structure on the slide, then the EM failure location is usually near the left end of a narrow segment.

October 13, 2009

Q: Is there a specification for overdrive on probe cards?

A: There is not a specification per se, but there are best practices. The best practice on pads in the 80-100 micron size use 75 microns of overdrive. For pads in the 30-50 micron range, an overdrive of 35-50 microns is more appropriate. Overdrive refers to overdrive in the z-axis.

September 03, 2009

Q: Where can I find some current papers on NBTI?

A: The best place to find information on the NBTI mechanism is in the Proceedings of the International Reliability Physics Symposium. The most important papers can be found in the last 6-7 years of proceedings, as it has become a major issue in recent years. We also have a good summary with reference to key papers in our Online Training system, http://www.semitracks.com/online-training/.

August 03, 2009

Q: Is it possible for conductive die epoxy to become non-conductive? What conditions are necessary for the epoxy to become conductive? Is it conductive in X,Y and Z directions when the grain size of silver is connected in a specific direction?

A: Conductive epoxy adhesives usually set up their conductivity in a planar manner. Silver additive is normally in a flake format and forms a set of platelets that provide that planar structure. Cure shrinkage of the base epoxy resin compresses the silver particles to make mechanical contact with each other.

As far as losing conductivity, it could result from (1) thermomechanical delamination, (2) poor or no initial curing, or (3) separation of silver through either (a) initial resin bleed or (b) incomplete pre-mixing.

July 06, 2009

Q: Devices are expected to withstand some amount of voltage/current stress; that's why input protection is included in all designs. How can I determine if EOS/ESD damage results from excessive stress conditions, a manufacturing defect, or an abnormal process variation? The question pertains to already damaged units, not virgin units.

A: I would suspect an abnormal process variation if the device fails in a manner (exhibits damage in a location) that is inconsistent with the results from the in-house EOS/ESD testing. For example, the customer return device might have failed due to a gate oxide rupture, but NSC testing on comparison ICs indicates that the ESD clamp always fails. However, this cannot necessarily be determined by examining the damage site. One can envision a defect in the ESD clamp that causes a failure in the customer device. Maybe it simply fails at a lower voltage than it should. Your best bet is to characterize ICs from the same lot, or even from the same wafer, to see if they fail in a manner similar to the returned IC.

June 01, 2009

Q: I had a question about multiple contacts. Design software often allows for additional contacts if there is room. Is there any reason not to have multiple contacts? Also is there any difference between Al and Cu?

A: As with many things in the semiconductor industry, it depends. Usually, adding more contacts increases electromigration lifetime. However, the graph below shows a situation where it doesn't.

In some cases, you can get a bimodal distribution. You still have early failures because the line, rather than the via, fails. This can be the case with both copper and aluminum. This is usually an issue when the shunt layer sheet resistance exceeds the via resistance.